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library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 
 
--  Uncomment the following lines to use the declarations that are 
--  provided for instantiating Xilinx primitive components. 
--library UNISIM; 
--use UNISIM.VComponents.all; 
 
entity uartrec is 
    Port (clk:in std_logic; 
		rxd:in std_logic; 
		RxAv:out std_logic; 
		data:out std_logic_vector(7 downto 0)); 
end uartrec; 
 
architecture Behavioral of uartrec is 
type state is (idle,work,tobuf); 
signal present_state:state; 
 
component BUFG
    port (I: in std_logic; O: out std_logic);
end component; 
 
component IBUF
    port (I: in std_logic; O: out std_logic);
end component; 
signal rxdbuf:std_logic; 
signal rxdin:std_logic; 
 
signal recclk:std_logic; 
signal data_buf:std_logic_vector(7 downto 0); 
signal cnt:integer range 0 to 4; 
signal divcnt:integer range 0 to 86; 
signal bitpos:integer range 0 to 7; 
begin 
 
u0:IBUF port map(I =>rxd,O =>rxdbuf); 
 
u1:BUFG port map(I =>rxdbuf,O =>rxdin); 
 
process(clk) 
begin 
  if clk'event and clk='1' then 
    if divcnt=86 then 
      divcnt<=0; 
	 recclk<='1'; 
    else 
      divcnt<=divcnt+1; 
	 recclk<='0'; 
    end if; 
  end if; 
end process; 
 
process(recclk) 
begin 
  if recclk'event and recclk='1' then 
    case present_state is 
      when idle => 
	   RxAv<='1'; 
	   if rxdin='1' then 
	     cnt<=0; 
	     present_state<=idle; 
	   else  
		cnt<=cnt+1; 
		if cnt=2 then 
		  present_state<=work; 
		  cnt<=0; 
		  bitpos<=0; 
		end if; 
	   end if; 
	 when work => 
	   if cnt=4 then 
	     cnt<=0; 
	     data_buf(bitpos)<=rxdin; 
		bitpos<=bitpos+1; 
		if bitpos=7 then 
		  bitpos<=0; 
		  present_state<=tobuf; 
		end if; 
	   else 
	     cnt<=cnt+1; 
	   end if; 
	 when tobuf => 
	   data<=data_buf; 
	   RxAv<='0'; 
	   present_state<=idle; 
    end case; 
  end if; 
end process; 
 
end Behavioral;