www.pudn.com > Exp6-VGA.rar > top.twr

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Release 6.2i Trace G.28 
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved. 
 
E:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml top top.ncd -o top.twr 
top.pcf 
 
 
Design file:              top.ncd 
Physical constraint file: top.pcf 
Device,speed:             xc2v1000,-4 (PRODUCTION 1.117 2003-12-13, STEPPING level 0) 
Report level:             error report 
 
Environment Variable      Effect  
--------------------      ------  
NONE                      No environment variables were set 
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INFO:Timing:2698 - No timing constraints found, doing default enumeration. 
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report. 
 
 
Data Sheet report: 
----------------- 
All values displayed in nanoseconds (ns) 
 
Clock to Setup on destination clock clk 
---------------+---------+---------+---------+---------+ 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall| 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| 
---------------+---------+---------+---------+---------+ 
clk            |    3.993|         |         |         | 
---------------+---------+---------+---------+---------+ 
 
Analysis completed Fri Jun 23 11:35:33 2006 
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Peak Memory Usage: 70 MB