www.pudn.com > Exp6-VGA.rar > top.syr
Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
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--> Reading design: top.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) HDL Analysis
4) HDL Synthesis
5) Advanced HDL Synthesis
5.1) HDL Synthesis Report
6) Low Level Synthesis
7) Final Report
7.1) Device utilization summary
7.2) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : top.prj
Input Format : mixed
Ignore Synthesis Constraint File : NO
Verilog Include Directory :
---- Target Parameters
Output File Name : top
Output Format : NGC
Target Device : xc2v1000-4-fg456
---- Source Options
Top Module Name : top
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
ROM Style : Auto
Mux Extraction : YES
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
Resource Sharing : YES
Multiplier Style : auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 16
Register Duplication : YES
Equivalent register Removal : YES
Slice Packing : YES
Pack IO Registers into IOBs : auto
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Keep Hierarchy : NO
Global Optimization : AllClockNets
RTL Output : Yes
Write Timing Constraints : NO
Hierarchy Separator : _
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
Slice Utilization Ratio Delta : 5
---- Other Options
lso : top.lso
Read Cores : YES
cross_clock_analysis : NO
verilog2001 : YES
Optimize Instantiated Primitives : NO
tristate2logic : No
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
WARNING:HDLParsers:3215 - Unit work/TOP is now defined in a different file: was G:/doc/lab6/top.vhd, now is E:/FPGA/Exp6-VGA/top.vhd
WARNING:HDLParsers:3215 - Unit work/TOP/BEHAVIORAL is now defined in a different file: was G:/doc/lab6/top.vhd, now is E:/FPGA/Exp6-VGA/top.vhd
WARNING:HDLParsers:3215 - Unit work/VGA is now defined in a different file: was G:/doc/lab6/vga.vhd, now is E:/FPGA/Exp6-VGA/vga.vhd
WARNING:HDLParsers:3215 - Unit work/VGA/BEHAVIORAL is now defined in a different file: was G:/doc/lab6/vga.vhd, now is E:/FPGA/Exp6-VGA/vga.vhd
WARNING:HDLParsers:3215 - Unit work/WRLOGO is now defined in a different file: was G:/doc/lab6/wrlogo.vhd, now is E:/FPGA/Exp6-VGA/wrlogo.vhd
WARNING:HDLParsers:3215 - Unit work/WRLOGO/BEHAVIORAL is now defined in a different file: was G:/doc/lab6/wrlogo.vhd, now is E:/FPGA/Exp6-VGA/wrlogo.vhd
WARNING:HDLParsers:3481 - No primary, secondary unit in the file E:\FPGA\Exp6-VGA/logo.vhd. Ignore this file from project file top_vhdl.prj.
WARNING:HDLParsers:3215 - Unit work/UARTREC is now defined in a different file: was G:/doc/lab6/uartrec.vhd, now is E:/FPGA/Exp6-VGA/uartrec.vhd
WARNING:HDLParsers:3215 - Unit work/UARTREC/BEHAVIORAL is now defined in a different file: was G:/doc/lab6/uartrec.vhd, now is E:/FPGA/Exp6-VGA/uartrec.vhd
Compiling vhdl file E:/FPGA/Exp6-VGA/uartrec.vhd in Library work.
Architecture behavioral of Entity uartrec is up to date.
Compiling vhdl file E:/FPGA/Exp6-VGA/wrlogo.vhd in Library work.
Architecture behavioral of Entity wrlogo is up to date.
Compiling vhdl file E:/FPGA/Exp6-VGA/vga.vhd in Library work.
Architecture behavioral of Entity vga is up to date.
Compiling vhdl file E:/FPGA/Exp6-VGA/top.vhd in Library work.
Architecture behavioral of Entity top is up to date.
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity (Architecture ).
INFO:Xst:1739 - HDL ADVISOR - E:/FPGA/Exp6-VGA/top.vhd line 15: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - E:/FPGA/Exp6-VGA/top.vhd line 16: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - E:/FPGA/Exp6-VGA/top.vhd line 14: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - E:/FPGA/Exp6-VGA/top.vhd line 15: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
WARNING:Xst:819 - E:/FPGA/Exp6-VGA/top.vhd line 112: The following signals are missing in the process sensitivity list:
data_sram.
WARNING:Xst:819 - E:/FPGA/Exp6-VGA/top.vhd line 121: The following signals are missing in the process sensitivity list:
data_ram, data_srambuf.
Entity analyzed. Unit generated.
Analyzing Entity (Architecture ).
WARNING:Xst:766 - E:/FPGA/Exp6-VGA/uartrec.vhd line 39: Generating a Black Box for component .
WARNING:Xst:766 - E:/FPGA/Exp6-VGA/uartrec.vhd line 41: Generating a Black Box for component .
Entity analyzed. Unit generated.
Analyzing Entity (Architecture ).
WARNING:Xst:819 - E:/FPGA/Exp6-VGA/wrlogo.vhd line 43: The following signals are missing in the process sensitivity list:
webuf, RxAv, readclk.
WARNING:Xst:766 - E:/FPGA/Exp6-VGA/wrlogo.vhd line 107: Generating a Black Box for component .
Entity analyzed. Unit generated.
Analyzing Entity (Architecture ).
WARNING:Xst:819 - E:/FPGA/Exp6-VGA/vga.vhd line 47: The following signals are missing in the process sensitivity list:
hs.
Entity analyzed. Unit generated.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit .
Related source file is E:/FPGA/Exp6-VGA/vga.vhd.
Found 11-bit comparator greatequal for signal <$n0007> created at line 58.
Found 11-bit comparator less for signal <$n0008> created at line 58.
Found 11-bit comparator greatequal for signal <$n0009> created at line 63.
Found 11-bit comparator less for signal <$n0010> created at line 63.
Found 10-bit up counter for signal .
Found 1-bit register for signal .
Found 10-bit up counter for signal .
Summary:
inferred 2 Counter(s).
inferred 1 D-type flip-flop(s).
inferred 4 Comparator(s).
Unit synthesized.
Synthesizing Unit .
Related source file is E:/FPGA/Exp6-VGA/wrlogo.vhd.
Found 8-bit register for signal .
Found 1-bit register for signal .
Found 3-bit adder for signal <$n0014> created at line 67.
Found 4-bit adder for signal <$n0015> created at line 67.
Found 10-bit comparator greatequal for signal <$n0019> created at line 99.
Found 10-bit comparator greatequal for signal <$n0020> created at line 67.
Found 10-bit comparator less for signal <$n0021> created at line 67.
Found 10-bit comparator greatequal for signal <$n0022> created at line 67.
Found 10-bit comparator less for signal <$n0023> created at line 67.
Found 13-bit adder for signal <$n0024> created at line 75.
Found 10-bit comparator lessequal for signal <$n0025> created at line 95.
Found 13-bit register for signal .
Found 10-bit register for signal .
Found 10-bit register for signal .
Found 10-bit up accumulator for signal .
Found 10-bit up accumulator for signal .
Found 1-bit register for signal .
Found 1-bit register for signal .
Found 1 1-bit 2-to-1 multiplexers.
Summary:
inferred 2 Accumulator(s).
inferred 24 D-type flip-flop(s).
inferred 3 Adder/Subtracter(s).
inferred 6 Comparator(s).
inferred 1 Multiplexer(s).
Unit synthesized.
Synthesizing Unit .
Related source file is E:/FPGA/Exp6-VGA/uartrec.vhd.
Found finite state machine for signal .
-----------------------------------------------------------------------
| States | 3 |
| Transitions | 7 |
| Inputs | 4 |
| Outputs | 3 |
| Clock | recclk (rising_edge) |
| Power Up State | idle |
| Encoding | automatic |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 1-bit register for signal .
Found 8-bit register for signal .
Found 3-bit adder for signal <$n0025> created at line 59.
Found 3-bit adder for signal <$n0026> created at line 77.
Found 3-bit register for signal .
Found 3-bit register for signal .
Found 8-bit register for signal .
Found 7-bit up counter for signal .
Found 1-bit register for signal .
Summary:
inferred 1 Finite State Machine(s).
inferred 1 Counter(s).
inferred 24 D-type flip-flop(s).
inferred 2 Adder/Subtracter(s).
Unit synthesized.
Synthesizing Unit .
Related source file is E:/FPGA/Exp6-VGA/top.vhd.
WARNING:Xst:646 - Signal is assigned but never used.
WARNING:Xst:653 - Signal is used but never assigned. Tied to value 00000000.
WARNING:Xst:1780 - Signal is never used or assigned.
WARNING:Xst:1780 - Signal is never used or assigned.
WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0.
Found 8 1-bit 2-to-1 multiplexers.
Summary:
inferred 8 Multiplexer(s).
Unit synthesized.
INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Advanced RAM inference ...
Advanced multiplier inference ...
Selecting encoding for FSM_0 ...
Optimizing FSM on signal with one-hot encoding.
Dynamic shift register inference ...
=========================================================================
HDL Synthesis Report
Macro Statistics
# FSMs : 1
# Adders/Subtractors : 5
13-bit adder : 1
4-bit adder : 1
3-bit adder : 3
# Counters : 3
10-bit up counter : 2
7-bit up counter : 1
# Accumulators : 2
10-bit up accumulator : 2
# Registers : 24
3-bit register : 2
1-bit register : 17
8-bit register : 2
13-bit register : 1
10-bit register : 2
# Comparators : 10
10-bit comparator lessequal : 1
10-bit comparator less : 2
10-bit comparator greatequal : 3
11-bit comparator less : 2
11-bit comparator greatequal : 2
# Multiplexers : 2
8-bit 2-to-1 multiplexer : 1
1-bit 2-to-1 multiplexer : 1
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Launcher: "logo.ngo" is up to date.
Loading core for timing and area information for instance .
WARNING:Xst:1291 - FF/Latch is unconnected in block .
Optimizing unit ...
Optimizing unit ...
Optimizing unit ...
Optimizing unit ...
WARNING:Xst:1710 - FF/Latch (without init value) is constant in block .
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) is constant in block .
Loading device for application Xst from file '2v1000.nph' in environment E:/Xilinx.
Mapping all equations...
WARNING:Xst:1291 - FF/Latch is unconnected in block .
Building and optimizing final netlist ...
Register u1_inc_y_1 equivalent to u1_inc_y_9 has been removed
Register u1_inc_y_3 equivalent to u1_inc_y_9 has been removed
Register u1_inc_y_4 equivalent to u1_inc_y_9 has been removed
Register u1_inc_y_5 equivalent to u1_inc_y_9 has been removed
Register u1_inc_y_6 equivalent to u1_inc_y_9 has been removed
Register u1_inc_y_7 equivalent to u1_inc_y_9 has been removed
Register u1_inc_y_8 equivalent to u1_inc_y_9 has been removed
Register u1_inc_y_2 equivalent to u1_inc_y_9 has been removed
Register u1_inc_x_1 equivalent to u1_inc_x_9 has been removed
Register u1_inc_x_3 equivalent to u1_inc_x_9 has been removed
Register u1_inc_x_4 equivalent to u1_inc_x_9 has been removed
Register u1_inc_x_5 equivalent to u1_inc_x_9 has been removed
Register u1_inc_x_6 equivalent to u1_inc_x_9 has been removed
Register u1_inc_x_7 equivalent to u1_inc_x_9 has been removed
Register u1_inc_x_8 equivalent to u1_inc_x_9 has been removed
Register u1_inc_x_2 equivalent to u1_inc_x_9 has been removed
Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 2.
WARNING:Xst:382 - Register BU42 is equivalent to BU12
WARNING:Xst:382 - Register BU72 is equivalent to BU12
WARNING:Xst:382 - Register BU102 is equivalent to BU12
WARNING:Xst:382 - Register BU132 is equivalent to BU12
WARNING:Xst:382 - Register BU162 is equivalent to BU12
WARNING:Xst:382 - Register BU192 is equivalent to BU12
WARNING:Xst:382 - Register BU222 is equivalent to BU12
WARNING:Xst:382 - Register BU72 is equivalent to BU42
WARNING:Xst:382 - Register BU102 is equivalent to BU42
WARNING:Xst:382 - Register BU132 is equivalent to BU42
WARNING:Xst:382 - Register BU162 is equivalent to BU42
WARNING:Xst:382 - Register BU192 is equivalent to BU42
WARNING:Xst:382 - Register BU222 is equivalent to BU42
WARNING:Xst:382 - Register BU102 is equivalent to BU72
WARNING:Xst:382 - Register BU132 is equivalent to BU72
WARNING:Xst:382 - Register BU162 is equivalent to BU72
WARNING:Xst:382 - Register BU192 is equivalent to BU72
WARNING:Xst:382 - Register BU222 is equivalent to BU72
WARNING:Xst:382 - Register BU132 is equivalent to BU102
WARNING:Xst:382 - Register BU162 is equivalent to BU102
WARNING:Xst:382 - Register BU192 is equivalent to BU102
WARNING:Xst:382 - Register BU222 is equivalent to BU102
WARNING:Xst:382 - Register BU162 is equivalent to BU132
WARNING:Xst:382 - Register BU192 is equivalent to BU132
WARNING:Xst:382 - Register BU222 is equivalent to BU132
WARNING:Xst:382 - Register BU192 is equivalent to BU162
WARNING:Xst:382 - Register BU222 is equivalent to BU162
WARNING:Xst:382 - Register BU222 is equivalent to BU192
FlipFlop u4_vlocbuf_9 has been replicated 1 time(s)
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : top.ngr
Top Level Output File Name : top
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 13
Macro Statistics :
# Registers : 60
# 1-bit register : 54
# 13-bit register : 1
# 3-bit register : 2
# 7-bit register : 1
# 8-bit register : 2
# Counters : 2
# 10-bit up counter : 2
# Multiplexers : 2
# 2-to-1 multiplexer : 2
# Adders/Subtractors : 4
# 10-bit adder : 2
# 13-bit adder : 1
# 7-bit adder : 1
# Comparators : 10
# 10-bit comparator greatequal: 3
# 10-bit comparator less : 2
# 10-bit comparator lessequal : 1
# 11-bit comparator greatequal: 2
# 11-bit comparator less : 2
Cell Usage :
# BELS : 368
# GND : 2
# LUT1 : 10
# LUT1_L : 16
# LUT2 : 54
# LUT2_L : 20
# LUT3 : 10
# LUT3_D : 1
# LUT3_L : 6
# LUT4 : 60
# LUT4_D : 6
# LUT4_L : 27
# MUXCY : 96
# MUXF5 : 2
# VCC : 2
# XORCY : 56
# FlipFlops/Latches : 109
# FD : 7
# FDC : 15
# FDCE : 15
# FDCPE : 21
# FDE : 32
# FDP : 5
# FDPE : 1
# FDR : 10
# FDS : 3
# RAMS : 16
# RAMB4_S1 : 16
# Clock Buffers : 2
# BUFG : 1
# BUFGP : 1
# IO Buffers : 12
# IBUF : 2
# OBUF : 10
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 2v1000fg456-4
Number of Slices: 120 out of 5120 2%
Number of Slice Flip Flops: 109 out of 10240 1%
Number of 4 input LUTs: 210 out of 10240 2%
Number of bonded IOBs: 12 out of 324 3%
Number of BRAMs: 16 out of 40 40%
Number of GCLKs: 2 out of 16 12%
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP | 10 |
hs_OBUF(u4_hs:O) | NONE(*)(u4_vlocbuf_4) | 11 |
u0_recclk:Q | NONE | 26 |
u4_vgaclk:Q | NONE | 10 |
u1_ramclk(u1_Mmux_ramclk_Result1:O)| NONE(*)(u1_u0/B215) | 46 |
u4_vlocbuf_9:Q | NONE | 10 |
u4_vlocbuf_9_1:Q | NONE | 12 |
-----------------------------------+------------------------+-------+
(*) These 2 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
Timing Summary:
---------------
Speed Grade: -4
Minimum period: 5.567ns (Maximum Frequency: 179.630MHz)
Minimum input arrival time before clock: 6.029ns
Maximum output required time after clock: 8.592ns
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay: 3.938ns (Levels of Logic = 8)
Source: u0_divcnt_0 (FF)
Destination: u0_divcnt_6 (FF)
Source Clock: clk rising
Destination Clock: clk rising
Data Path: u0_divcnt_0 to u0_divcnt_6
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDR:C->Q 3 0.568 0.724 u0_divcnt_0 (u0_divcnt_0)
LUT1_L:I0->LO 2 0.439 0.000 u0_divcnt_Madd__n0000_inst_lut2_01 (u0_divcnt_Madd__n0000_inst_lut2_0)
MUXCY:S->O 1 0.298 0.000 u0_divcnt_Madd__n0000_inst_cy_0 (u0_divcnt_Madd__n0000_inst_cy_0)
MUXCY:CI->O 1 0.053 0.000 u0_divcnt_Madd__n0000_inst_cy_1 (u0_divcnt_Madd__n0000_inst_cy_1)
MUXCY:CI->O 1 0.053 0.000 u0_divcnt_Madd__n0000_inst_cy_2 (u0_divcnt_Madd__n0000_inst_cy_2)
MUXCY:CI->O 1 0.053 0.000 u0_divcnt_Madd__n0000_inst_cy_3 (u0_divcnt_Madd__n0000_inst_cy_3)
MUXCY:CI->O 1 0.053 0.000 u0_divcnt_Madd__n0000_inst_cy_4 (u0_divcnt_Madd__n0000_inst_cy_4)
MUXCY:CI->O 0 0.053 0.000 u0_divcnt_Madd__n0000_inst_cy_5 (u0_divcnt_Madd__n0000_inst_cy_5)
XORCY:CI->O 1 1.274 0.000 u0_divcnt_Madd__n0000_inst_sum_6 (u0_divcnt__n0000<6>)
FDR:D 0.370 u0_divcnt_6
----------------------------------------
Total 3.938ns (3.214ns logic, 0.724ns route)
(81.6% logic, 18.4% route)
-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'u4_hs:O'
Delay: 5.567ns (Levels of Logic = 13)
Source: u4_vlocbuf_9 (FF)
Destination: u4_vlocbuf_9 (FF)
Source Clock: u4_hs:O rising
Destination Clock: u4_hs:O rising
Data Path: u4_vlocbuf_9 to u4_vlocbuf_9
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCPE:C->Q 14 0.568 0.977 u4_vlocbuf_9 (u4_vlocbuf_9)
LUT4:I0->O 3 0.439 0.724 u4__n000411 (CHOICE732)
LUT4_D:I0->LO 1 0.439 0.000 u4__n000434 (N12987)
MUXCY:S->O 1 0.298 0.000 u4_vlocbuf_inst_cy_7 (u4_vlocbuf_inst_cy_7)
MUXCY:CI->O 1 0.053 0.000 u4_vlocbuf_inst_cy_8 (u4_vlocbuf_inst_cy_8)
MUXCY:CI->O 1 0.053 0.000 u4_vlocbuf_inst_cy_9 (u4_vlocbuf_inst_cy_9)
MUXCY:CI->O 1 0.053 0.000 u4_vlocbuf_inst_cy_10 (u4_vlocbuf_inst_cy_10)
MUXCY:CI->O 1 0.053 0.000 u4_vlocbuf_inst_cy_11 (u4_vlocbuf_inst_cy_11)
MUXCY:CI->O 1 0.053 0.000 u4_vlocbuf_inst_cy_12 (u4_vlocbuf_inst_cy_12)
MUXCY:CI->O 1 0.053 0.000 u4_vlocbuf_inst_cy_13 (u4_vlocbuf_inst_cy_13)
MUXCY:CI->O 1 0.053 0.000 u4_vlocbuf_inst_cy_14 (u4_vlocbuf_inst_cy_14)
MUXCY:CI->O 1 0.053 0.000 u4_vlocbuf_inst_cy_15 (u4_vlocbuf_inst_cy_15)
MUXCY:CI->O 0 0.053 0.000 u4_vlocbuf_inst_cy_16 (u4_vlocbuf_inst_cy_16)
XORCY:CI->O 2 1.274 0.000 u4_vlocbuf_inst_sum_16 (u4_vlocbuf_inst_sum_16)
FDCPE:D 0.370 u4_vlocbuf_9
----------------------------------------
Total 5.567ns (3.865ns logic, 1.702ns route)
(69.4% logic, 30.6% route)
-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'u0_recclk:Q'
Delay: 4.504ns (Levels of Logic = 3)
Source: u0_present_state_FFd3 (FF)
Destination: u0_cnt_1 (FF)
Source Clock: u0_recclk:Q rising
Destination Clock: u0_recclk:Q rising
Data Path: u0_present_state_FFd3 to u0_cnt_1
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 4 0.568 0.747 u0_present_state_FFd3 (u0_present_state_FFd3)
LUT2:I0->O 1 0.439 0.517 u0_Ker518018 (CHOICE606)
MUXF5:S->O 3 0.699 0.724 u0_Ker518025 (u0_N5182)
LUT4_L:I3->LO 1 0.439 0.000 u0__n0015<1>1 (u0__n0015<1>)
FD:D 0.370 u0_cnt_1
----------------------------------------
Total 4.504ns (2.515ns logic, 1.989ns route)
(55.8% logic, 44.2% route)
-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'u4_vgaclk:Q'
Delay: 5.452ns (Levels of Logic = 13)
Source: u4_hlocbuf_6 (FF)
Destination: u4_hlocbuf_9 (FF)
Source Clock: u4_vgaclk:Q rising
Destination Clock: u4_vgaclk:Q rising
Data Path: u4_hlocbuf_6 to u4_hlocbuf_9
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCPE:C->Q 5 0.568 0.771 u4_hlocbuf_6 (u4_hlocbuf_6)
LUT4:I0->O 7 0.439 0.816 u4__n00038 (CHOICE719)
LUT4_D:I0->LO 1 0.439 0.000 u4__n000325 (N12930)
MUXCY:S->O 1 0.298 0.000 u4_hlocbuf_inst_cy_7 (u4_hlocbuf_inst_cy_7)
MUXCY:CI->O 1 0.053 0.000 u4_hlocbuf_inst_cy_8 (u4_hlocbuf_inst_cy_8)
MUXCY:CI->O 1 0.053 0.000 u4_hlocbuf_inst_cy_9 (u4_hlocbuf_inst_cy_9)
MUXCY:CI->O 1 0.053 0.000 u4_hlocbuf_inst_cy_10 (u4_hlocbuf_inst_cy_10)
MUXCY:CI->O 1 0.053 0.000 u4_hlocbuf_inst_cy_11 (u4_hlocbuf_inst_cy_11)
MUXCY:CI->O 1 0.053 0.000 u4_hlocbuf_inst_cy_12 (u4_hlocbuf_inst_cy_12)
MUXCY:CI->O 1 0.053 0.000 u4_hlocbuf_inst_cy_13 (u4_hlocbuf_inst_cy_13)
MUXCY:CI->O 1 0.053 0.000 u4_hlocbuf_inst_cy_14 (u4_hlocbuf_inst_cy_14)
MUXCY:CI->O 1 0.053 0.000 u4_hlocbuf_inst_cy_15 (u4_hlocbuf_inst_cy_15)
MUXCY:CI->O 0 0.053 0.000 u4_hlocbuf_inst_cy_16 (u4_hlocbuf_inst_cy_16)
XORCY:CI->O 1 1.274 0.000 u4_hlocbuf_inst_sum_16 (u4_hlocbuf_inst_sum_16)
FDCPE:D 0.370 u4_hlocbuf_9
----------------------------------------
Total 5.452ns (3.865ns logic, 1.587ns route)
(70.9% logic, 29.1% route)
-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'u1_Mmux_ramclk_Result1:O'
Delay: 5.523ns (Levels of Logic = 15)
Source: u1_addr_0 (FF)
Destination: u1_addr_12 (FF)
Source Clock: u1_Mmux_ramclk_Result1:O rising
Destination Clock: u1_Mmux_ramclk_Result1:O rising
Data Path: u1_addr_0 to u1_addr_12
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCE:C->Q 19 0.568 1.035 u1_addr_0 (u1_addr_0)
LUT1_L:I0->LO 1 0.439 0.000 u1_Madd__n0024_inst_lut2_371 (u1_Madd__n0024_inst_lut2_37)
MUXCY:S->O 1 0.298 0.000 u1_Madd__n0024_inst_cy_47 (u1_Madd__n0024_inst_cy_47)
MUXCY:CI->O 1 0.053 0.000 u1_Madd__n0024_inst_cy_48 (u1_Madd__n0024_inst_cy_48)
MUXCY:CI->O 1 0.053 0.000 u1_Madd__n0024_inst_cy_49 (u1_Madd__n0024_inst_cy_49)
MUXCY:CI->O 1 0.053 0.000 u1_Madd__n0024_inst_cy_50 (u1_Madd__n0024_inst_cy_50)
MUXCY:CI->O 1 0.053 0.000 u1_Madd__n0024_inst_cy_51 (u1_Madd__n0024_inst_cy_51)
MUXCY:CI->O 1 0.053 0.000 u1_Madd__n0024_inst_cy_52 (u1_Madd__n0024_inst_cy_52)
MUXCY:CI->O 1 0.053 0.000 u1_Madd__n0024_inst_cy_53 (u1_Madd__n0024_inst_cy_53)
MUXCY:CI->O 1 0.053 0.000 u1_Madd__n0024_inst_cy_54 (u1_Madd__n0024_inst_cy_54)
MUXCY:CI->O 1 0.053 0.000 u1_Madd__n0024_inst_cy_55 (u1_Madd__n0024_inst_cy_55)
MUXCY:CI->O 1 0.053 0.000 u1_Madd__n0024_inst_cy_56 (u1_Madd__n0024_inst_cy_56)
MUXCY:CI->O 1 0.053 0.000 u1_Madd__n0024_inst_cy_57 (u1_Madd__n0024_inst_cy_57)
MUXCY:CI->O 0 0.053 0.000 u1_Madd__n0024_inst_cy_58 (u1_Madd__n0024_inst_cy_58)
XORCY:CI->O 1 1.274 0.517 u1_Madd__n0024_inst_sum_39 (u1__n0024<12>)
LUT4_L:I0->LO 1 0.439 0.000 u1__n0000<12>1 (u1__n0000<12>)
FDCE:D 0.370 u1_addr_12
----------------------------------------
Total 5.523ns (3.971ns logic, 1.552ns route)
(71.9% logic, 28.1% route)
-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'u4_vlocbuf_9:Q'
Delay: 4.076ns (Levels of Logic = 8)
Source: u1_inc_x_9 (FF)
Destination: u1_mov_x_7 (FF)
Source Clock: u4_vlocbuf_9:Q rising
Destination Clock: u4_vlocbuf_9:Q rising
Data Path: u1_inc_x_9 to u1_mov_x_7
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCE:C->Q 9 0.568 0.862 u1_inc_x_9 (u1_inc_x_9)
LUT2_L:I0->LO 1 0.439 0.000 u1_mov_x_Madd__n0000_inst_lut2_81 (u1_mov_x_Madd__n0000_inst_lut2_8)
MUXCY:S->O 1 0.298 0.000 u1_mov_x_Madd__n0000_inst_cy_19 (u1_mov_x_Madd__n0000_inst_cy_19)
MUXCY:CI->O 1 0.053 0.000 u1_mov_x_Madd__n0000_inst_cy_20 (u1_mov_x_Madd__n0000_inst_cy_20)
MUXCY:CI->O 1 0.053 0.000 u1_mov_x_Madd__n0000_inst_cy_21 (u1_mov_x_Madd__n0000_inst_cy_21)
MUXCY:CI->O 1 0.053 0.000 u1_mov_x_Madd__n0000_inst_cy_22 (u1_mov_x_Madd__n0000_inst_cy_22)
MUXCY:CI->O 1 0.053 0.000 u1_mov_x_Madd__n0000_inst_cy_23 (u1_mov_x_Madd__n0000_inst_cy_23)
MUXCY:CI->O 1 0.053 0.000 u1_mov_x_Madd__n0000_inst_cy_24 (u1_mov_x_Madd__n0000_inst_cy_24)
XORCY:CI->O 1 1.274 0.000 u1_mov_x_Madd__n0000_inst_sum_24 (u1_mov_x__n0000<7>)
FDC:D 0.370 u1_mov_x_7
----------------------------------------
Total 4.076ns (3.214ns logic, 0.862ns route)
(78.8% logic, 21.2% route)
-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'u4_vlocbuf_9_1:Q'
Delay: 4.120ns (Levels of Logic = 11)
Source: u1_mov_y_0 (FF)
Destination: u1_mov_y_9 (FF)
Source Clock: u4_vlocbuf_9_1:Q rising
Destination Clock: u4_vlocbuf_9_1:Q rising
Data Path: u1_mov_y_0 to u1_mov_y_9
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC:C->Q 4 0.568 0.747 u1_mov_y_0 (u1_mov_y_0)
LUT1_L:I0->LO 2 0.439 0.000 u1_mov_y_Madd__n0000_inst_lut2_711 (u1_mov_y_Madd__n0000_inst_lut2_7)
MUXCY:S->O 1 0.298 0.000 u1_mov_y_Madd__n0000_inst_cy_18 (u1_mov_y_Madd__n0000_inst_cy_18)
MUXCY:CI->O 1 0.053 0.000 u1_mov_y_Madd__n0000_inst_cy_19 (u1_mov_y_Madd__n0000_inst_cy_19)
MUXCY:CI->O 1 0.053 0.000 u1_mov_y_Madd__n0000_inst_cy_20 (u1_mov_y_Madd__n0000_inst_cy_20)
MUXCY:CI->O 1 0.053 0.000 u1_mov_y_Madd__n0000_inst_cy_21 (u1_mov_y_Madd__n0000_inst_cy_21)
MUXCY:CI->O 1 0.053 0.000 u1_mov_y_Madd__n0000_inst_cy_22 (u1_mov_y_Madd__n0000_inst_cy_22)
MUXCY:CI->O 1 0.053 0.000 u1_mov_y_Madd__n0000_inst_cy_23 (u1_mov_y_Madd__n0000_inst_cy_23)
MUXCY:CI->O 1 0.053 0.000 u1_mov_y_Madd__n0000_inst_cy_24 (u1_mov_y_Madd__n0000_inst_cy_24)
MUXCY:CI->O 1 0.053 0.000 u1_mov_y_Madd__n0000_inst_cy_25 (u1_mov_y_Madd__n0000_inst_cy_25)
MUXCY:CI->O 0 0.053 0.000 u1_mov_y_Madd__n0000_inst_cy_26 (u1_mov_y_Madd__n0000_inst_cy_26)
XORCY:CI->O 1 1.274 0.000 u1_mov_y_Madd__n0000_inst_sum_26 (u1_mov_y__n0000<9>)
FDC:D 0.370 u1_mov_y_9
----------------------------------------
Total 4.120ns (3.373ns logic, 0.747ns route)
(81.9% logic, 18.1% route)
-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'u0_recclk:Q'
Offset: 6.029ns (Levels of Logic = 5)
Source: rxd (PAD)
Destination: u0_cnt_1 (FF)
Destination Clock: u0_recclk:Q rising
Data Path: rxd to u0_cnt_1
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 1 0.825 0.517 u0_u0 (u0_rxdbuf)
BUFG:I->O 11 0.589 0.909 u0_u1 (u0_rxdin)
LUT2:I1->O 1 0.439 0.517 u0_Ker518018 (CHOICE606)
MUXF5:S->O 3 0.699 0.724 u0_Ker518025 (u0_N5182)
LUT4_L:I3->LO 1 0.439 0.000 u0__n0015<1>1 (u0__n0015<1>)
FD:D 0.370 u0_cnt_1
----------------------------------------
Total 6.029ns (3.361ns logic, 2.668ns route)
(55.7% logic, 44.3% route)
-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'u1_Mmux_ramclk_Result1:O'
Offset: 3.045ns (Levels of Logic = 2)
Source: rst (PAD)
Destination: u1_dout_7 (FF)
Destination Clock: u1_Mmux_ramclk_Result1:O rising
Data Path: rst to u1_dout_7
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 2 0.825 0.702 rst_IBUF (rst_IBUF)
LUT2:I0->O 8 0.439 0.839 u1__n00091 (u1__n0009)
FDE:CE 0.240 u1_dout_1
----------------------------------------
Total 3.045ns (1.504ns logic, 1.541ns route)
(49.4% logic, 50.6% route)
-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'u4_vgaclk:Q'
Offset: 8.027ns (Levels of Logic = 3)
Source: u4_hlocbuf_8 (FF)
Destination: hs (PAD)
Source Clock: u4_vgaclk:Q rising
Data Path: u4_hlocbuf_8 to hs
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCPE:C->Q 5 0.568 0.771 u4_hlocbuf_8 (u4_hlocbuf_8)
LUT3:I0->O 1 0.439 0.517 u4_hs_SW0 (N11657)
LUT4:I0->O 12 0.439 0.931 u4_hs (hs_OBUF)
OBUF:I->O 4.361 hs_OBUF (hs)
----------------------------------------
Total 8.027ns (5.807ns logic, 2.220ns route)
(72.3% logic, 27.7% route)
-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'u4_hs:O'
Offset: 8.592ns (Levels of Logic = 4)
Source: u4_vlocbuf_2 (FF)
Destination: vs (PAD)
Source Clock: u4_hs:O rising
Data Path: u4_vlocbuf_2 to vs
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCPE:C->Q 6 0.568 0.793 u4_vlocbuf_2 (u4_vlocbuf_2)
LUT3:I0->O 1 0.439 0.517 u4_vs37_SW1 (N12902)
LUT4:I3->O 1 0.439 0.517 u4_vs37 (CHOICE585)
LUT2:I1->O 1 0.439 0.517 u4_vs48 (vs_OBUF)
OBUF:I->O 4.361 vs_OBUF (vs)
----------------------------------------
Total 8.592ns (6.246ns logic, 2.346ns route)
(72.7% logic, 27.3% route)
-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'u1_Mmux_ramclk_Result1:O'
Offset: 5.446ns (Levels of Logic = 1)
Source: u1_dout_7 (FF)
Destination: rgb<7> (PAD)
Source Clock: u1_Mmux_ramclk_Result1:O rising
Data Path: u1_dout_7 to rgb<7>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDE:C->Q 1 0.568 0.517 u1_dout_7 (u1_dout_7)
OBUF:I->O 4.361 rgb_7_OBUF (rgb<7>)
----------------------------------------
Total 5.446ns (4.929ns logic, 0.517ns route)
(90.5% logic, 9.5% route)
=========================================================================
CPU : 16.64 / 18.08 s | Elapsed : 17.00 / 18.00 s
-->
Total memory usage is 81896 kilobytes