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# Xilinx CORE Generator 5.2.03i 
# Username = Administrator 
# COREGenPath = C:\Xilinx\coregen 
# ProjectPath = D:\vgashow 
# ExpandedProjectPath = D:\vgashow 
# OverwriteFiles = true 
# Core name: logo 
# Number of Primitives in design: 48 
# Number of CLBs used in design cannot be determined when there is no RPMed logic 
# Number of Slices used in design cannot be determined when there is no RPMed logic 
# Number of LUT sites used in design: 24 
# Number of LUTs used in design: 24 
# Number of REG used in design: 8 
# Number of SRL16s used in design: 0 
# Number of Distributed RAM primitives used in design: 0 
# Number of Block Memories used in design: 16 
# Number of Dedicated Multipliers cannot be determined when there is no RPMed logic 
# Number of HU_SETs used: 0 
#  
SET BusFormat = BusFormatAngleBracket 
SET SimulationOutputProducts = Verilog VHDL 
SET XilinxFamily = Spartan2 
SET OutputOption = DesignFlow 
SET DesignFlow = Vhdl 
SET FlowVendor = Foundation_iSE 
SET FormalVerification = None 
SELECT Single_Port_Block_Memory Spartan2 Xilinx,_Inc. 5.0 
CSET primitive_selection = Optimize_For_Area 
CSET init_value = 0 
CSET register_inputs = false 
CSET write_enable_polarity = Active_High 
CSET init_pin = false 
CSET initialization_pin_polarity = Active_High 
CSET global_init_value = 0 
CSET select_primitive = 4kx1 
CSET enable_pin = false 
CSET write_mode = Read_After_Write 
CSET port_configuration = Read_And_Write 
CSET component_name = logo 
CSET active_clock_edge = Rising_Edge_Triggered 
CSET handshaking_pins = false 
CSET width = 8 
CSET load_init_file = false 
CSET enable_pin_polarity = Active_High 
CSET additional_output_pipe_stages = 0 
CSET has_limit_data_pitch = false 
CSET limit_data_pitch = 8 
CSET depth = 8192 
GENERATE