www.pudn.com > Exp6-VGA.rar > logo.v

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// The synopsys directives "translate_off/translate_on" specified 
// below are supported by XST, FPGA Express, Exemplar and Synplicity 
// synthesis tools. Ensure they are correct for your synthesis tool(s). 
 
// You must compile the wrapper file logo.v when simulating 
// the core, logo. When compiling the wrapper file, be sure to 
// reference the XilinxCoreLib Verilog simulation library. For detailed 
// instructions, please refer to the "Coregen Users Guide". 
 
module logo ( 
	addr, 
	clk, 
	din, 
	dout, 
	we);    // synthesis black_box 
 
input [12 : 0] addr; 
input clk; 
input [7 : 0] din; 
output [7 : 0] dout; 
input we; 
 
// synopsys translate_off 
 
	BLKMEMSP_V5_0 #( 
		13,	// c_addr_width 
		"0",	// c_default_data 
		8192,	// c_depth 
		0,	// c_enable_rlocs 
		1,	// c_has_default_data 
		1,	// c_has_din 
		0,	// c_has_en 
		0,	// c_has_limit_data_pitch 
		0,	// c_has_nd 
		0,	// c_has_rdy 
		0,	// c_has_rfd 
		0,	// c_has_sinit 
		1,	// c_has_we 
		8,	// c_limit_data_pitch 
		"mif_file_16_1",	// c_mem_init_file 
		0,	// c_pipe_stages 
		0,	// c_reg_inputs 
		"0",	// c_sinit_value 
		8,	// c_width 
		0,	// c_write_mode 
		"0",	// c_ybottom_addr 
		1,	// c_yclk_is_rising 
		1,	// c_yen_is_high 
		"hierarchy1",	// c_yhierarchy 
		0,	// c_ymake_bmm 
		"4kx1",	// c_yprimitive_type 
		1,	// c_ysinit_is_high 
		"1024",	// c_ytop_addr 
		0,	// c_yuse_single_primitive 
		1)	// c_ywe_is_high 
	inst ( 
		.ADDR(addr), 
		.CLK(clk), 
		.DIN(din), 
		.DOUT(dout), 
		.WE(we), 
		.EN(), 
		.ND(), 
		.RFD(), 
		.RDY(), 
		.SINIT()); 
 
 
// synopsys translate_on 
 
// FPGA Express black box declaration 
// synopsys attribute fpga_dont_touch "true" 
// synthesis attribute fpga_dont_touch of logo is "true" 
 
// XST black box declaration 
// box_type "black_box" 
// synthesis attribute box_type of logo is "black_box" 
 
endmodule