www.pudn.com > Exp6-VGA.rar > ground.coregen_log

# Xilinx CORE Generator 5.2.03i 
# User = Administrator 
# Initializing default project... 
# Loading plug-ins... 
# Initializing GUI... 
SETPROJECT D:\vgashow 
# lockprojectprops=false 
# busformat=BusFormatAngleBracket 
# designflow=Vhdl 
# expandedprojectpath=D:\vgashow 
# flowvendor=Foundation_iSE 
# formalverification=None 
# simulationoutputproducts=Verilog VHDL 
# xilinxfamily=Spartan2 
# outputoption=DesignFlow 
# overwritefiles=Default 
# expandedprojectpath=D:\vgashow 
# Set current Project to D:\vgashow 
SELECT Single_Port_Block_Memory Spartan2 Xilinx,_Inc. 5.0 
CSET Write_Mode = Read_After_Write 
CSET Enable_Pin = false 
CSET Active_Clock_Edge = Rising_Edge_Triggered 
CSET Limit_Data_Pitch = 8 
CSET Depth = 19200 
CSET Write_Enable_polarity = Active_High 
CSET Global_Init_Value = 0 
CSET Additional_Output_Pipe_Stages = 0 
CSET Select_Primitive = 4kx1 
CSET Init_Pin = false 
CSET Init_Value = 0 
CSET Port_Configuration = Read_And_Write 
CSET Component_Name = ground 
CSET Initialization_Pin_Polarity = Active_High 
CSET Primitive_Selection = Optimize_For_Area 
CSET Register_Inputs = false 
CSET Has_Limit_Data_Pitch = false 
CSET Handshaking_Pins = false 
CSET Width = 8 
CSET Load_Init_File = false 
CSET Enable_Pin_Polarity = Active_High 
GENERATE 
# Preparing to elaborate core... 
# Elaborating the module... 
# Generating the core .EDN implementation netlist... 
# Generating the .VHO/.VHD simulation support files... 
# Generating the .VEO/.V simulation support files... 
# Generating the .ASY symbol file... 
# Generating ISE symbol file... 
# Executing: C:\Xilinx\bin\nt\coresupt.exe D:\vgashow\ground.asy 
# Execution Complete.  Return code: 0 
# Successfully generated ground (Single Port Block Memory 5.0) 
# Successfully generated  (Single Port Block Memory 5.0) 
#   
END