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[COREGEN.VHDL Component Instantiation.logo] 
type=template 
text000=" " 
text001=" " 
text002="-- The following code must appear in the VHDL architecture header:" 
text003=" " 
text004="component logo" 
text005="    port (" 
text006="    addr: IN std_logic_VECTOR(12 downto 0);" 
text007="    clk: IN std_logic;" 
text008="    din: IN std_logic_VECTOR(7 downto 0);" 
text009="    dout: OUT std_logic_VECTOR(7 downto 0);" 
text010="    we: IN std_logic);" 
text011="end component;" 
text012="" 
text013="" 
text014="" 
text015="" 
text016=" " 
text017="-------------------------------------------------------------" 
text018=" " 
text019="-- The following code must appear in the VHDL architecture body." 
text020="-- Substitute your own instance name and net names." 
text021=" " 
text022="your_instance_name : logo" 
text023="        port map (" 
text024="            addr => addr," 
text025="            clk => clk," 
text026="            din => din," 
text027="            dout => dout," 
text028="            we => we);" 
text029=" " 
[COREGEN.VERILOG Component Instantiation.logo] 
type=template 
text000=" " 
text001=" " 
text002="// The following must be inserted into your Verilog file for this" 
text003="// core to be instantiated. Change the instance name and port connections" 
text004="// (in parentheses) to your own signal names." 
text005=" " 
text006="logo YourInstanceName (" 
text007="    .addr(addr)," 
text008="    .clk(clk)," 
text009="    .din(din)," 
text010="    .dout(dout)," 
text011="    .we(we));" 
text012="" 
text013=" " 
[COREGEN.VHDL Component Instantiation.ground] 
type=template 
text000=" " 
text001=" " 
text002="-- The following code must appear in the VHDL architecture header:" 
text003=" " 
text004="component ground" 
text005="    port (" 
text006="    addr: IN std_logic_VECTOR(0 downto 0);" 
text007="    clk: IN std_logic;" 
text008="    din: IN std_logic_VECTOR(7 downto 0);" 
text009="    dout: OUT std_logic_VECTOR(7 downto 0);" 
text010="    we: IN std_logic);" 
text011="end component;" 
text012="" 
text013="" 
text014="" 
text015="" 
text016=" " 
text017="-------------------------------------------------------------" 
text018=" " 
text019="-- The following code must appear in the VHDL architecture body." 
text020="-- Substitute your own instance name and net names." 
text021=" " 
text022="your_instance_name : ground" 
text023="        port map (" 
text024="            addr => addr," 
text025="            clk => clk," 
text026="            din => din," 
text027="            dout => dout," 
text028="            we => we);" 
text029=" " 
[COREGEN.VERILOG Component Instantiation.ground] 
type=template 
text000=" " 
text001=" " 
text002="// The following must be inserted into your Verilog file for this" 
text003="// core to be instantiated. Change the instance name and port connections" 
text004="// (in parentheses) to your own signal names." 
text005=" " 
text006="ground YourInstanceName (" 
text007="    .addr(addr)," 
text008="    .clk(clk)," 
text009="    .din(din)," 
text010="    .dout(dout)," 
text011="    .we(we));" 
text012="" 
text013=" "