www.pudn.com > RS422_receive.rar > RS422_receive.v, change:2013-07-26,size:5307b


`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: tianye
// 
// Create Date:    09:25:22 03/01/2013 
// Design Name:    tianye
// Module Name:    RS422_receive 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module RS422_receive(
    input gclk,               //gloable clock 
    input Rx_data,            //uart in data
    input rst,                //signal of reset
    output reg [7:0] data_out,    //data of receive
    output reg data_err,          //process in receive is error 
    output reg data_rdy,           //receiving data is over and the data is ready to be received
	 output reg data_rec
    );

//reg [7:0] data_out;
//reg data_err;
//reg data_rdy;
//reg data_rec;
reg [3:0] state;
reg [3:0] count_rate;
reg [3:0] count_data;
reg [7:0] shiftreg;
reg parity_check;

parameter waiting = 3'b000;
parameter start = 3'b001;
parameter shift = 3'b010;
parameter receive = 3'b011;
parameter parity = 3'b100;
parameter dataend = 3'b101;

always@(posedge gclk)
begin
	if (rst==1'b0)
	begin
		state <= waiting;
		data_out <= 8'h00;
		data_rdy <= 1'b0;
		data_err <= 1'b0;
		data_rec <= 1'b0;
		count_rate <= 4'b0000;
		count_data <= 4'b0000;
		shiftreg <= 8'h00;
		parity_check <= 1'b0;
	end
	else 
	begin	
		case(state)
		waiting:
		begin
			if (Rx_data == 1'b1)
			begin
				state <= waiting;
				data_rdy <= 1'b0;
				data_err <= 1'b0;
				data_rec <= 1'b0;
				count_rate <= 4'b0000;
				count_data <= 4'b0000;
				shiftreg <= 8'h00;
				parity_check <= 1'b0;
			end
			else
			begin
				state <= start;
				data_rdy <= 1'b0;
				data_err <= 1'b0;
				data_rec <= 1'b0;
				count_rate <= 1'b0;
				count_data <= 4'b0000;
				shiftreg <= 8'h00;
			end
		end
		
		start:
		begin
			if((count_rate == 4'b0101)||(count_rate == 4'b1000))
			begin
				if(Rx_data == 1'b1)
				begin
					state <= waiting;
					data_rdy <= 1'b0;
					data_err <= 1'b0;
					count_rate <=4'b0000;
					count_data <= 4'b0000;
					shiftreg <= 8'h00;
				end
				else
				begin
					state <= start;
					data_rdy <= 1'b0;
					data_err <= 1'b0;
					count_rate <= count_rate + 1'b1;
					count_data <= 4'b0000;
					shiftreg <= 8'h00;
				end
			end
			else if(count_rate == 4'b1001)
			begin
				//if(Rx_data == 1'b0)
				//begin
					state <= shift;
					data_rdy <= 1'b0;
					data_err <= 1'b0;
					data_rec <= 1'b1;
					count_rate <=4'b0000;
					count_data <= 4'b0000;
					shiftreg <= 8'h00;
				end
				/*else
				begin
					state <= waiting;
					data_rdy <= 1'b0;
					data_err <= 1'b0;
					data_rec <= 1'b0;
					count_rate <=4'b0000;
					count_data <= 4'b0000;
					shiftreg <= 8'h00;
				end
			end*/
			else
			begin
				state <= state;
				data_rdy <= 1'b0;
				data_err <= 1'b0;
				data_rec <= 1'b0;
				count_rate <= count_rate + 1'b1;
				count_data <= 4'b0000;
				shiftreg <= 8'h00;
			end
		end
		
		shift:
		begin
			if(count_data == 4'b1000)
			begin
				state <= parity;
				data_rec <= 1'b0;
				count_rate <= count_rate + 1'b1;
				count_data <= count_data;
				shiftreg <= shiftreg;
			end
			else
			begin
				state <= receive;
				data_rec <= 1'b0;
				count_rate <= count_rate + 1'b1;
				count_data <= count_data;
				shiftreg[7:1] <= shiftreg[6:0];
			end
		end
		
		receive:
		begin
			if(count_rate == 4'b1000)
			begin
				state <= state;
				count_rate <= count_rate + 1'b1;
				count_data <= count_data + 1'b1;
				shiftreg[0] <= Rx_data;
				data_rec <= 1'b1;
				parity_check <= parity_check ^ Rx_data;
			end
			else if(count_rate == 4'b1001)
			begin
				state <= shift;
				data_rec <= 1'b0;
				count_rate <= 1'b0;
				count_data <= count_data;
			end
			else
			begin
				state <= state;
				data_rec <= 1'b0;
				count_rate <= count_rate + 1'b1;
				count_data <= count_data;
			end
		end
		
		parity:
		begin
			if(count_rate == 4'b1000)
			begin
				state <= state;
				data_rec <= 1'b0;
				count_rate <= count_rate + 1'b1;
				count_data <= count_data;
				if(parity_check == Rx_data)
					data_err <= 1'b0;
				else	
					data_err <= 1'b1;				
			end
			else if(count_rate == 4'b1001)
			begin
				state <= dataend;
				data_rec <= 1'b0;
				count_rate <= 4'b0000;
				count_data <= count_data;
			end
			else
			begin
				state <= state;
				data_rec <= 1'b0;
				count_rate <= count_rate + 1'b1;
				count_data <= count_data;
			end
		end
		
		dataend:
		begin
			if(data_err == 1'b1)
			begin
			  state <= waiting;
			  data_rdy <= 1'b0;
			end
			else if(count_rate == 4'b1000)
			begin
				if(Rx_data == 1'b0)
				begin
					state <= waiting;
					data_err <= 1'b1;
					data_rdy <= 1'b0;
				end
				else
				begin
					state <= state;
					count_rate <= count_rate + 1'b1;
					count_data <= count_data;
					data_rdy <= 1'b1;
					data_out <= shiftreg;
				end
			end
			else if(count_rate == 4'b1001)
				state <= waiting;
			else
			begin
				state <= state;
				count_rate <= count_rate + 1'b1;
				count_data <= count_data;
				data_err <= data_err;
				data_rdy <= data_rdy;
			end
		end
		
		default:
			state <= start;
			
	endcase
					
				
	end
end	

endmodule