000000c6 <__bad_interrupt>: c6: 0c 94 00 00 jmp 0x0 <__vectors> 000000ca : // BASIC_RF_RX_INFO* // The pointer to the next BASIC_RF_RX_INFO structure to be used by the FIFOP ISR. If there is // only one buffer, then return pRRI. //------------------------------------------------------------------------------------------------------- BASIC_RF_RX_INFO* basicRfReceivePacket(BASIC_RF_RX_INFO *pRRI) { ca: cf 93 push r28 cc: df 93 push r29 ce: cd b7 in r28, 0x3d ; 61 d0: de b7 in r29, 0x3e ; 62 d2: 22 97 sbiw r28, 0x02 ; 2 d4: 0f b6 in r0, 0x3f ; 63 d6: f8 94 cli d8: de bf out 0x3e, r29 ; 62 da: 0f be out 0x3f, r0 ; 63 dc: cd bf out 0x3d, r28 ; 61 de: 9a 83 std Y+2, r25 ; 0x02 e0: 89 83 std Y+1, r24 ; 0x01 // Adjust the led brightness PWM0_SET_DUTY_CYCLE(pRRI->pPayload[0]); e2: e9 81 ldd r30, Y+1 ; 0x01 e4: fa 81 ldd r31, Y+2 ; 0x02 e6: 06 80 ldd r0, Z+6 ; 0x06 e8: f7 81 ldd r31, Z+7 ; 0x07 ea: e0 2d mov r30, r0 ec: 80 81 ld r24, Z ee: 80 93 51 00 sts 0x0051, r24 // Blink the green LED SET_GLED(); f2: 80 91 23 00 lds r24, 0x0023 f6: 84 60 ori r24, 0x04 ; 4 f8: 80 93 23 00 sts 0x0023, r24 halWait(50000); fc: 80 e5 ldi r24, 0x50 ; 80 fe: 93 ec ldi r25, 0xC3 ; 195 100: 0e 94 3a 01 call 0x274 CLR_GLED();//PB7 104: 80 91 23 00 lds r24, 0x0023 108: 8b 7f andi r24, 0xFB ; 251 10a: 80 93 23 00 sts 0x0023, r24 //FASTSPI_STROBE(CC2420_SACK); // Continue using the (one and only) reception structure return pRRI; 10e: 89 81 ldd r24, Y+1 ; 0x01 110: 9a 81 ldd r25, Y+2 ; 0x02 112: 22 96 adiw r28, 0x02 ; 2 114: 0f b6 in r0, 0x3f ; 63 116: f8 94 cli 118: de bf out 0x3e, r29 ; 62 11a: 0f be out 0x3f, r0 ; 63 11c: cd bf out 0x3d, r28 ; 61 11e: df 91 pop r29 120: cf 91 pop r28 122: 08 95 ret 00000124

: } // basicRfReceivePacket //------------------------------------------------------------------------------------------------------- // void main (void) // // DESCRIPTION: // Startup routine and main loop //------------------------------------------------------------------------------------------------------- int main (void) { 124: ce ef ldi r28, 0xFE ; 254 126: d0 e1 ldi r29, 0x10 ; 16 128: de bf out 0x3e, r29 ; 62 12a: cd bf out 0x3d, r28 ; 61 // UINT16 ledDutyCycle, dimmerDifference; UINT8 n; // BYTE spiStatusByte; // Initalize ports for communication with CC2420 and other peripheral units Mcu_INIT(); 12c: f8 94 cli 12e: 10 92 5c 00 sts 0x005C, r1 132: 10 92 6d 00 sts 0x006D, r1 136: 10 92 6c 00 sts 0x006C, r1 13a: 80 e8 ldi r24, 0x80 ; 128 13c: 80 93 55 00 sts 0x0055, r24 140: 78 94 sei PORT_INIT(); 142: f8 94 cli 144: 86 e0 ldi r24, 0x06 ; 6 146: 80 93 40 00 sts 0x0040, r24 14a: 10 92 3b 00 sts 0x003B, r1 14e: 8f ef ldi r24, 0xFF ; 255 150: 80 93 3a 00 sts 0x003A, r24 154: 10 92 38 00 sts 0x0038, r1 158: 10 92 37 00 sts 0x0037, r1 15c: 87 e7 ldi r24, 0x77 ; 119 15e: 80 93 37 00 sts 0x0037, r24 162: 87 e4 ldi r24, 0x47 ; 71 164: 80 93 38 00 sts 0x0038, r24 168: 10 92 35 00 sts 0x0035, r1 16c: 8f ef ldi r24, 0xFF ; 255 16e: 80 93 34 00 sts 0x0034, r24 172: 10 92 32 00 sts 0x0032, r1 176: 10 92 31 00 sts 0x0031, r1 17a: 10 92 23 00 sts 0x0023, r1 17e: 10 92 22 00 sts 0x0022, r1 182: 8e e0 ldi r24, 0x0E ; 14 184: 80 93 22 00 sts 0x0022, r24 188: 10 92 23 00 sts 0x0023, r1 18c: 80 e4 ldi r24, 0x40 ; 64 18e: 80 93 61 00 sts 0x0061, r24 192: 78 94 sei SPI_INIT(); 194: f8 94 cli 196: 80 e5 ldi r24, 0x50 ; 80 198: 80 93 2d 00 sts 0x002D, r24 19c: 81 e0 ldi r24, 0x01 ; 1 19e: 80 93 2e 00 sts 0x002E, r24 1a2: 78 94 sei SET_GLED(); 1a4: 80 91 23 00 lds r24, 0x0023 1a8: 84 60 ori r24, 0x04 ; 4 1aa: 80 93 23 00 sts 0x0023, r24 SET_OLED(); 1ae: 80 91 38 00 lds r24, 0x0038 1b2: 80 61 ori r24, 0x10 ; 16 1b4: 80 93 38 00 sts 0x0038, r24 SET_RLED(); 1b8: 80 91 23 00 lds r24, 0x0023 1bc: 88 60 ori r24, 0x08 ; 8 1be: 80 93 23 00 sts 0x0023, r24 SET_YLED(); 1c2: 80 91 23 00 lds r24, 0x0023 1c6: 82 60 ori r24, 0x02 ; 2 1c8: 80 93 23 00 sts 0x0023, r24 halWait(50000); 1cc: 80 e5 ldi r24, 0x50 ; 80 1ce: 93 ec ldi r25, 0xC3 ; 195 1d0: 0e 94 3a 01 call 0x274 CLR_GLED(); 1d4: 80 91 23 00 lds r24, 0x0023 1d8: 8b 7f andi r24, 0xFB ; 251 1da: 80 93 23 00 sts 0x0023, r24 CLR_OLED(); 1de: 80 91 38 00 lds r24, 0x0038 1e2: 8f 7e andi r24, 0xEF ; 239 1e4: 80 93 38 00 sts 0x0038, r24 CLR_YLED(); 1e8: 80 91 23 00 lds r24, 0x0023 1ec: 8d 7f andi r24, 0xFD ; 253 1ee: 80 93 23 00 sts 0x0023, r24 CLR_RLED(); 1f2: 80 91 23 00 lds r24, 0x0023 1f6: 87 7f andi r24, 0xF7 ; 247 1f8: 80 93 23 00 sts 0x0023, r24 // Initialize PWM0 with a period of CLK/1024 PWM0_INIT(TIMER_CLK_DIV1024); 1fc: 10 92 51 00 sts 0x0051, r1 200: 88 e7 ldi r24, 0x78 ; 120 202: 80 93 53 00 sts 0x0053, r24 206: 80 91 53 00 lds r24, 0x0053 20a: 88 7f andi r24, 0xF8 ; 248 20c: 87 60 ori r24, 0x07 ; 7 20e: 80 93 53 00 sts 0x0053, r24 // Initialize and enable the ADC for reading the pot meter //ADC_INIT(); // ADC_SET_CHANNEL(ADC_INPUT_0_POT_METER); //ADC_ENABLE(); // Wait for the user to select node address, and initialize for basic RF operation basicRfInit(&rfRxInfo, 26, 0x2420, 0x0001); 212: 21 e0 ldi r18, 0x01 ; 1 214: 30 e0 ldi r19, 0x00 ; 0 216: 40 e2 ldi r20, 0x20 ; 32 218: 54 e2 ldi r21, 0x24 ; 36 21a: 6a e1 ldi r22, 0x1A ; 26 21c: 80 e0 ldi r24, 0x00 ; 0 21e: 91 e0 ldi r25, 0x01 ; 1 220: 0e 94 de 01 call 0x3bc rfTxInfo.destAddr = 0x0000; 224: 10 92 81 01 sts 0x0181, r1 228: 10 92 80 01 sts 0x0180, r1 // Initalize common protocol parameters rfTxInfo.length = 10; 22c: 8a e0 ldi r24, 0x0A ; 10 22e: 80 93 82 01 sts 0x0182, r24 rfTxInfo.ackRequest = TRUE; 232: 81 e0 ldi r24, 0x01 ; 1 234: 80 93 85 01 sts 0x0185, r24 rfTxInfo.pPayload = pTxBuffer; 238: 86 e8 ldi r24, 0x86 ; 134 23a: 91 e0 ldi r25, 0x01 ; 1 23c: 90 93 84 01 sts 0x0184, r25 240: 80 93 83 01 sts 0x0183, r24 rfRxInfo.pPayload = pRxBuffer; 244: 8a e0 ldi r24, 0x0A ; 10 246: 91 e0 ldi r25, 0x01 ; 1 248: 90 93 07 01 sts 0x0107, r25 24c: 80 93 06 01 sts 0x0106, r24 for (n = 0; n < 10; n++) 250: 19 82 std Y+1, r1 ; 0x01 252: 89 81 ldd r24, Y+1 ; 0x01 254: 8a 30 cpi r24, 0x0A ; 10 256: 58 f4 brcc .+22 ; 0x26e { pTxBuffer[n] = n; 258: 89 81 ldd r24, Y+1 ; 0x01 25a: 99 27 eor r25, r25 25c: fc 01 movw r30, r24 25e: ea 57 subi r30, 0x7A ; 122 260: fe 4f sbci r31, 0xFE ; 254 262: 89 81 ldd r24, Y+1 ; 0x01 264: 80 83 st Z, r24 266: 89 81 ldd r24, Y+1 ; 0x01 268: 8f 5f subi r24, 0xFF ; 255 26a: 89 83 std Y+1, r24 ; 0x01 26c: f2 cf rjmp .-28 ; 0x252 } //Turn on RX mode basicRfReceiveOn(); 26e: 0e 94 59 05 call 0xab2 for(;;); 272: ff cf rjmp .-2 ; 0x272 00000274 : // ARGUMENTS: // UINT16 timeout // The timeout in microseconds //------------------------------------------------------------------------------------------------------- void halWait(UINT16 timeout) { 274: cf 93 push r28 276: df 93 push r29 278: cd b7 in r28, 0x3d ; 61 27a: de b7 in r29, 0x3e ; 62 27c: 22 97 sbiw r28, 0x02 ; 2 27e: 0f b6 in r0, 0x3f ; 63 280: f8 94 cli 282: de bf out 0x3e, r29 ; 62 284: 0f be out 0x3f, r0 ; 63 286: cd bf out 0x3d, r28 ; 61 288: 9a 83 std Y+2, r25 ; 0x02 28a: 89 83 std Y+1, r24 ; 0x01 ... // This sequence uses exactly 8 clock cycle for each round do { NOP(); NOP(); NOP(); NOP(); } while (--timeout); 294: 89 81 ldd r24, Y+1 ; 0x01 296: 9a 81 ldd r25, Y+2 ; 0x02 298: 01 97 sbiw r24, 0x01 ; 1 29a: 9a 83 std Y+2, r25 ; 0x02 29c: 89 83 std Y+1, r24 ; 0x01 29e: 00 97 sbiw r24, 0x00 ; 0 2a0: 09 f0 breq .+2 ; 0x2a4 2a2: f4 cf rjmp .-24 ; 0x28c 2a4: 22 96 adiw r28, 0x02 ; 2 2a6: 0f b6 in r0, 0x3f ; 63 2a8: f8 94 cli 2aa: de bf out 0x3e, r29 ; 62 2ac: 0f be out 0x3f, r0 ; 63 2ae: cd bf out 0x3d, r28 ; 61 2b0: df 91 pop r29 2b2: cf 91 pop r28 2b4: 08 95 ret 000002b6 : // PARAMETERS: // UINT8 channel // The channel number (11-26) //------------------------------------------------------------------------------------------------------- void halRfSetChannel(UINT8 channel) { 2b6: cf 93 push r28 2b8: df 93 push r29 2ba: cd b7 in r28, 0x3d ; 61 2bc: de b7 in r29, 0x3e ; 62 2be: 23 97 sbiw r28, 0x03 ; 3 2c0: 0f b6 in r0, 0x3f ; 63 2c2: f8 94 cli 2c4: de bf out 0x3e, r29 ; 62 2c6: 0f be out 0x3f, r0 ; 63 2c8: cd bf out 0x3d, r28 ; 61 2ca: 89 83 std Y+1, r24 ; 0x01 UINT16 f; // Derive frequency programming from the given channel number f = (UINT16) (channel - 11); // Subtract the base channel 2cc: 89 81 ldd r24, Y+1 ; 0x01 2ce: 99 27 eor r25, r25 2d0: 0b 97 sbiw r24, 0x0b ; 11 2d2: 9b 83 std Y+3, r25 ; 0x03 2d4: 8a 83 std Y+2, r24 ; 0x02 f = f + (f << 2); // Multiply with 5, which is the channel spacing 2d6: 8a 81 ldd r24, Y+2 ; 0x02 2d8: 9b 81 ldd r25, Y+3 ; 0x03 2da: 9c 01 movw r18, r24 2dc: 22 0f add r18, r18 2de: 33 1f adc r19, r19 2e0: 22 0f add r18, r18 2e2: 33 1f adc r19, r19 2e4: 8a 81 ldd r24, Y+2 ; 0x02 2e6: 9b 81 ldd r25, Y+3 ; 0x03 2e8: 82 0f add r24, r18 2ea: 93 1f adc r25, r19 2ec: 9b 83 std Y+3, r25 ; 0x03 2ee: 8a 83 std Y+2, r24 ; 0x02 f = f + 357 + 0x4000; // 357 is 2405-2048, 0x4000 is LOCK_THR = 1 2f0: 8a 81 ldd r24, Y+2 ; 0x02 2f2: 9b 81 ldd r25, Y+3 ; 0x03 2f4: 8b 59 subi r24, 0x9B ; 155 2f6: 9e 4b sbci r25, 0xBE ; 190 2f8: 9b 83 std Y+3, r25 ; 0x03 2fa: 8a 83 std Y+2, r24 ; 0x02 // Write it to the CC2420 DISABLE_GLOBAL_INT(); 2fc: f8 94 cli FASTSPI_SETREG(CC2420_FSCTRL, f); 2fe: 80 91 38 00 lds r24, 0x0038 302: 8e 7f andi r24, 0xFE ; 254 304: 80 93 38 00 sts 0x0038, r24 308: 88 e1 ldi r24, 0x18 ; 24 30a: 80 93 2f 00 sts 0x002F, r24 30e: 80 91 2e 00 lds r24, 0x002E 312: 88 23 and r24, r24 314: 0c f0 brlt .+2 ; 0x318 316: fb cf rjmp .-10 ; 0x30e 318: 8a 81 ldd r24, Y+2 ; 0x02 31a: 9b 81 ldd r25, Y+3 ; 0x03 31c: 89 2f mov r24, r25 31e: 99 27 eor r25, r25 320: 80 93 2f 00 sts 0x002F, r24 324: 80 91 2e 00 lds r24, 0x002E 328: 88 23 and r24, r24 32a: 0c f0 brlt .+2 ; 0x32e 32c: fb cf rjmp .-10 ; 0x324 32e: 8a 81 ldd r24, Y+2 ; 0x02 330: 80 93 2f 00 sts 0x002F, r24 334: 80 91 2e 00 lds r24, 0x002E 338: 88 23 and r24, r24 33a: 0c f0 brlt .+2 ; 0x33e 33c: fb cf rjmp .-10 ; 0x334 33e: 80 91 38 00 lds r24, 0x0038 342: 81 60 ori r24, 0x01 ; 1 344: 80 93 38 00 sts 0x0038, r24 ENABLE_GLOBAL_INT(); 348: 78 94 sei 34a: 23 96 adiw r28, 0x03 ; 3 34c: 0f b6 in r0, 0x3f ; 63 34e: f8 94 cli 350: de bf out 0x3e, r29 ; 62 352: 0f be out 0x3f, r0 ; 63 354: cd bf out 0x3d, r28 ; 61 356: df 91 pop r29 358: cf 91 pop r28 35a: 08 95 ret 0000035c : // Note that this function will lock up if the SXOSCON command strobe has not been given before the // function call. Also note that global interrupts will always be enabled when this function // returns. //------------------------------------------------------------------------------------------------------- void halRfWaitForCrystalOscillator(void) { 35c: cf 93 push r28 35e: df 93 push r29 360: cd b7 in r28, 0x3d ; 61 362: de b7 in r29, 0x3e ; 62 364: 21 97 sbiw r28, 0x01 ; 1 366: 0f b6 in r0, 0x3f ; 63 368: f8 94 cli 36a: de bf out 0x3e, r29 ; 62 36c: 0f be out 0x3f, r0 ; 63 36e: cd bf out 0x3d, r28 ; 61 BYTE spiStatusByte; // Poll the SPI status byte until the crystal oscillator is stable do { DISABLE_GLOBAL_INT(); 370: f8 94 cli FASTSPI_UPD_STATUS(spiStatusByte); 372: 80 91 38 00 lds r24, 0x0038 376: 8e 7f andi r24, 0xFE ; 254 378: 80 93 38 00 sts 0x0038, r24 37c: 10 92 2f 00 sts 0x002F, r1 380: 80 91 2e 00 lds r24, 0x002E 384: 88 23 and r24, r24 386: 0c f0 brlt .+2 ; 0x38a 388: fb cf rjmp .-10 ; 0x380 38a: 80 91 2f 00 lds r24, 0x002F 38e: 89 83 std Y+1, r24 ; 0x01 390: 80 91 38 00 lds r24, 0x0038 394: 81 60 ori r24, 0x01 ; 1 396: 80 93 38 00 sts 0x0038, r24 ENABLE_GLOBAL_INT(); 39a: 78 94 sei } while (!(spiStatusByte & (BM(CC2420_XOSC16M_STABLE)))); 39c: 89 81 ldd r24, Y+1 ; 0x01 39e: 99 27 eor r25, r25 3a0: 80 74 andi r24, 0x40 ; 64 3a2: 90 70 andi r25, 0x00 ; 0 3a4: 00 97 sbiw r24, 0x00 ; 0 3a6: 09 f4 brne .+2 ; 0x3aa 3a8: e3 cf rjmp .-58 ; 0x370 3aa: 21 96 adiw r28, 0x01 ; 1 3ac: 0f b6 in r0, 0x3f ; 63 3ae: f8 94 cli 3b0: de bf out 0x3e, r29 ; 62 3b2: 0f be out 0x3f, r0 ; 63 3b4: cd bf out 0x3d, r28 ; 61 3b6: df 91 pop r29 3b8: cf 91 pop r28 3ba: 08 95 ret 000003bc : // The 16-bit short address which is used by this node. Must together with the PAN ID form a // unique 32-bit identifier to avoid addressing conflicts. Normally, in a 802.15.4 network, the // short address will be given to associated nodes by the PAN coordinator. //------------------------------------------------------------------------------------------------------- void basicRfInit(BASIC_RF_RX_INFO *pRRI, UINT8 channel, WORD panId, WORD myAddr) { 3bc: cf 93 push r28 3be: df 93 push r29 3c0: cd b7 in r28, 0x3d ; 61 3c2: de b7 in r29, 0x3e ; 62 3c4: 28 97 sbiw r28, 0x08 ; 8 3c6: 0f b6 in r0, 0x3f ; 63 3c8: f8 94 cli 3ca: de bf out 0x3e, r29 ; 62 3cc: 0f be out 0x3f, r0 ; 63 3ce: cd bf out 0x3d, r28 ; 61 3d0: 9a 83 std Y+2, r25 ; 0x02 3d2: 89 83 std Y+1, r24 ; 0x01 3d4: 6b 83 std Y+3, r22 ; 0x03 3d6: 5d 83 std Y+5, r21 ; 0x05 3d8: 4c 83 std Y+4, r20 ; 0x04 3da: 3f 83 std Y+7, r19 ; 0x07 3dc: 2e 83 std Y+6, r18 ; 0x06 UINT8 n; // Make sure that the voltage regulator is on, and that the reset pin is inactive SET_VREG_ACTIVE(); 3de: 80 91 38 00 lds r24, 0x0038 3e2: 80 62 ori r24, 0x20 ; 32 3e4: 80 93 38 00 sts 0x0038, r24 halWait(1000); 3e8: 88 ee ldi r24, 0xE8 ; 232 3ea: 93 e0 ldi r25, 0x03 ; 3 3ec: 0e 94 3a 01 call 0x274 SET_RESET_ACTIVE(); 3f0: 80 91 38 00 lds r24, 0x0038 3f4: 8f 7b andi r24, 0xBF ; 191 3f6: 80 93 38 00 sts 0x0038, r24 halWait(1); 3fa: 81 e0 ldi r24, 0x01 ; 1 3fc: 90 e0 ldi r25, 0x00 ; 0 3fe: 0e 94 3a 01 call 0x274 SET_RESET_INACTIVE(); 402: 80 91 38 00 lds r24, 0x0038 406: 80 64 ori r24, 0x40 ; 64 408: 80 93 38 00 sts 0x0038, r24 halWait(5); 40c: 85 e0 ldi r24, 0x05 ; 5 40e: 90 e0 ldi r25, 0x00 ; 0 410: 0e 94 3a 01 call 0x274 // Initialize the FIFOP external interrupt FIFOP_INT_INIT(); 414: 80 91 6a 00 lds r24, 0x006A 418: 83 60 ori r24, 0x03 ; 3 41a: 80 93 6a 00 sts 0x006A, r24 41e: 80 91 58 00 lds r24, 0x0058 422: 8e 7f andi r24, 0xFE ; 254 424: 80 93 58 00 sts 0x0058, r24 ENABLE_FIFOP_INT(); 428: 80 91 59 00 lds r24, 0x0059 42c: 81 60 ori r24, 0x01 ; 1 42e: 80 93 59 00 sts 0x0059, r24 // Turn off all interrupts while we're accessing the CC2420 registers DISABLE_GLOBAL_INT(); 432: f8 94 cli // Register modifications FASTSPI_STROBE(CC2420_SXOSCON); 434: 80 91 38 00 lds r24, 0x0038 438: 8e 7f andi r24, 0xFE ; 254 43a: 80 93 38 00 sts 0x0038, r24 43e: 81 e0 ldi r24, 0x01 ; 1 440: 80 93 2f 00 sts 0x002F, r24 444: 80 91 2e 00 lds r24, 0x002E 448: 88 23 and r24, r24 44a: 0c f0 brlt .+2 ; 0x44e 44c: fb cf rjmp .-10 ; 0x444 44e: 80 91 38 00 lds r24, 0x0038 452: 81 60 ori r24, 0x01 ; 1 454: 80 93 38 00 sts 0x0038, r24 FASTSPI_SETREG(CC2420_MDMCTRL0, 0x0AF2); // Turn on automatic packet acknowledgment 458: 80 91 38 00 lds r24, 0x0038 45c: 8e 7f andi r24, 0xFE ; 254 45e: 80 93 38 00 sts 0x0038, r24 462: 81 e1 ldi r24, 0x11 ; 17 464: 80 93 2f 00 sts 0x002F, r24 468: 80 91 2e 00 lds r24, 0x002E 46c: 88 23 and r24, r24 46e: 0c f0 brlt .+2 ; 0x472 470: fb cf rjmp .-10 ; 0x468 472: 8a e0 ldi r24, 0x0A ; 10 474: 80 93 2f 00 sts 0x002F, r24 478: 80 91 2e 00 lds r24, 0x002E 47c: 88 23 and r24, r24 47e: 0c f0 brlt .+2 ; 0x482 480: fb cf rjmp .-10 ; 0x478 482: 82 ef ldi r24, 0xF2 ; 242 484: 80 93 2f 00 sts 0x002F, r24 488: 80 91 2e 00 lds r24, 0x002E 48c: 88 23 and r24, r24 48e: 0c f0 brlt .+2 ; 0x492 490: fb cf rjmp .-10 ; 0x488 492: 80 91 38 00 lds r24, 0x0038 496: 81 60 ori r24, 0x01 ; 1 498: 80 93 38 00 sts 0x0038, r24 FASTSPI_SETREG(CC2420_MDMCTRL1, 0x0500); // Set the correlation threshold = 20 49c: 80 91 38 00 lds r24, 0x0038 4a0: 8e 7f andi r24, 0xFE ; 254 4a2: 80 93 38 00 sts 0x0038, r24 4a6: 82 e1 ldi r24, 0x12 ; 18 4a8: 80 93 2f 00 sts 0x002F, r24 4ac: 80 91 2e 00 lds r24, 0x002E 4b0: 88 23 and r24, r24 4b2: 0c f0 brlt .+2 ; 0x4b6 4b4: fb cf rjmp .-10 ; 0x4ac 4b6: 85 e0 ldi r24, 0x05 ; 5 4b8: 80 93 2f 00 sts 0x002F, r24 4bc: 80 91 2e 00 lds r24, 0x002E 4c0: 88 23 and r24, r24 4c2: 0c f0 brlt .+2 ; 0x4c6 4c4: fb cf rjmp .-10 ; 0x4bc 4c6: 10 92 2f 00 sts 0x002F, r1 4ca: 80 91 2e 00 lds r24, 0x002E 4ce: 88 23 and r24, r24 4d0: 0c f0 brlt .+2 ; 0x4d4 4d2: fb cf rjmp .-10 ; 0x4ca 4d4: 80 91 38 00 lds r24, 0x0038 4d8: 81 60 ori r24, 0x01 ; 1 4da: 80 93 38 00 sts 0x0038, r24 FASTSPI_SETREG(CC2420_IOCFG0, 0x007F); // Set the FIFOP threshold to maximum 4de: 80 91 38 00 lds r24, 0x0038 4e2: 8e 7f andi r24, 0xFE ; 254 4e4: 80 93 38 00 sts 0x0038, r24 4e8: 8c e1 ldi r24, 0x1C ; 28 4ea: 80 93 2f 00 sts 0x002F, r24 4ee: 80 91 2e 00 lds r24, 0x002E 4f2: 88 23 and r24, r24 4f4: 0c f0 brlt .+2 ; 0x4f8 4f6: fb cf rjmp .-10 ; 0x4ee 4f8: 10 92 2f 00 sts 0x002F, r1 4fc: 80 91 2e 00 lds r24, 0x002E 500: 88 23 and r24, r24 502: 0c f0 brlt .+2 ; 0x506 504: fb cf rjmp .-10 ; 0x4fc 506: 8f e7 ldi r24, 0x7F ; 127 508: 80 93 2f 00 sts 0x002F, r24 50c: 80 91 2e 00 lds r24, 0x002E 510: 88 23 and r24, r24 512: 0c f0 brlt .+2 ; 0x516 514: fb cf rjmp .-10 ; 0x50c 516: 80 91 38 00 lds r24, 0x0038 51a: 81 60 ori r24, 0x01 ; 1 51c: 80 93 38 00 sts 0x0038, r24 FASTSPI_SETREG(CC2420_SECCTRL0, 0x01C4); // Turn off "Security enable" 520: 80 91 38 00 lds r24, 0x0038 524: 8e 7f andi r24, 0xFE ; 254 526: 80 93 38 00 sts 0x0038, r24 52a: 89 e1 ldi r24, 0x19 ; 25 52c: 80 93 2f 00 sts 0x002F, r24 530: 80 91 2e 00 lds r24, 0x002E 534: 88 23 and r24, r24 536: 0c f0 brlt .+2 ; 0x53a 538: fb cf rjmp .-10 ; 0x530 53a: 81 e0 ldi r24, 0x01 ; 1 53c: 80 93 2f 00 sts 0x002F, r24 540: 80 91 2e 00 lds r24, 0x002E 544: 88 23 and r24, r24 546: 0c f0 brlt .+2 ; 0x54a 548: fb cf rjmp .-10 ; 0x540 54a: 84 ec ldi r24, 0xC4 ; 196 54c: 80 93 2f 00 sts 0x002F, r24 550: 80 91 2e 00 lds r24, 0x002E 554: 88 23 and r24, r24 556: 0c f0 brlt .+2 ; 0x55a 558: fb cf rjmp .-10 ; 0x550 55a: 80 91 38 00 lds r24, 0x0038 55e: 81 60 ori r24, 0x01 ; 1 560: 80 93 38 00 sts 0x0038, r24 // Set the RF channel halRfSetChannel(channel); 564: 8b 81 ldd r24, Y+3 ; 0x03 566: 0e 94 5b 01 call 0x2b6 // Turn interrupts back on ENABLE_GLOBAL_INT(); 56a: 78 94 sei // Set the protocol configuration rfSettings.pRxInfo = pRRI; 56c: 89 81 ldd r24, Y+1 ; 0x01 56e: 9a 81 ldd r25, Y+2 ; 0x02 570: 90 93 fb 01 sts 0x01FB, r25 574: 80 93 fa 01 sts 0x01FA, r24 rfSettings.panId = panId; 578: 8c 81 ldd r24, Y+4 ; 0x04 57a: 9d 81 ldd r25, Y+5 ; 0x05 57c: 90 93 ff 01 sts 0x01FF, r25 580: 80 93 fe 01 sts 0x01FE, r24 rfSettings.myAddr = myAddr; 584: 8e 81 ldd r24, Y+6 ; 0x06 586: 9f 81 ldd r25, Y+7 ; 0x07 588: 90 93 01 02 sts 0x0201, r25 58c: 80 93 00 02 sts 0x0200, r24 rfSettings.txSeqNumber = 0; 590: 10 92 fc 01 sts 0x01FC, r1 rfSettings.receiveOn = FALSE; 594: 10 92 02 02 sts 0x0202, r1 // Wait for the crystal oscillator to become stable halRfWaitForCrystalOscillator(); 598: 0e 94 ae 01 call 0x35c // Write the short address and the PAN ID to the CC2420 RAM (requires that the XOSC is on and stable) DISABLE_GLOBAL_INT(); 59c: f8 94 cli FASTSPI_WRITE_RAM_LE(&myAddr, CC2420RAM_SHORTADDR, 2, n); 59e: 80 91 38 00 lds r24, 0x0038 5a2: 8e 7f andi r24, 0xFE ; 254 5a4: 80 93 38 00 sts 0x0038, r24 5a8: 8a ee ldi r24, 0xEA ; 234 5aa: 80 93 2f 00 sts 0x002F, r24 5ae: 80 91 2e 00 lds r24, 0x002E 5b2: 88 23 and r24, r24 5b4: 0c f0 brlt .+2 ; 0x5b8 5b6: fb cf rjmp .-10 ; 0x5ae 5b8: 80 e8 ldi r24, 0x80 ; 128 5ba: 80 93 2f 00 sts 0x002F, r24 5be: 80 91 2e 00 lds r24, 0x002E 5c2: 88 23 and r24, r24 5c4: 0c f0 brlt .+2 ; 0x5c8 5c6: fb cf rjmp .-10 ; 0x5be 5c8: 18 86 std Y+8, r1 ; 0x08 5ca: 88 85 ldd r24, Y+8 ; 0x08 5cc: 82 30 cpi r24, 0x02 ; 2 5ce: a8 f4 brcc .+42 ; 0x5fa 5d0: 88 85 ldd r24, Y+8 ; 0x08 5d2: 28 2f mov r18, r24 5d4: 33 27 eor r19, r19 5d6: ce 01 movw r24, r28 5d8: 01 96 adiw r24, 0x01 ; 1 5da: 82 0f add r24, r18 5dc: 93 1f adc r25, r19 5de: fc 01 movw r30, r24 5e0: 35 96 adiw r30, 0x05 ; 5 5e2: 80 81 ld r24, Z 5e4: 80 93 2f 00 sts 0x002F, r24 5e8: 80 91 2e 00 lds r24, 0x002E 5ec: 88 23 and r24, r24 5ee: 0c f0 brlt .+2 ; 0x5f2 5f0: fb cf rjmp .-10 ; 0x5e8 5f2: 88 85 ldd r24, Y+8 ; 0x08 5f4: 8f 5f subi r24, 0xFF ; 255 5f6: 88 87 std Y+8, r24 ; 0x08 5f8: e8 cf rjmp .-48 ; 0x5ca 5fa: 80 91 38 00 lds r24, 0x0038 5fe: 81 60 ori r24, 0x01 ; 1 600: 80 93 38 00 sts 0x0038, r24 FASTSPI_WRITE_RAM_LE(&panId, CC2420RAM_PANID, 2, n); 604: 80 91 38 00 lds r24, 0x0038 608: 8e 7f andi r24, 0xFE ; 254 60a: 80 93 38 00 sts 0x0038, r24 60e: 88 ee ldi r24, 0xE8 ; 232 610: 80 93 2f 00 sts 0x002F, r24 614: 80 91 2e 00 lds r24, 0x002E 618: 88 23 and r24, r24 61a: 0c f0 brlt .+2 ; 0x61e 61c: fb cf rjmp .-10 ; 0x614 61e: 80 e8 ldi r24, 0x80 ; 128 620: 80 93 2f 00 sts 0x002F, r24 624: 80 91 2e 00 lds r24, 0x002E 628: 88 23 and r24, r24 62a: 0c f0 brlt .+2 ; 0x62e 62c: fb cf rjmp .-10 ; 0x624 62e: 18 86 std Y+8, r1 ; 0x08 630: 88 85 ldd r24, Y+8 ; 0x08 632: 82 30 cpi r24, 0x02 ; 2 634: a8 f4 brcc .+42 ; 0x660 636: 88 85 ldd r24, Y+8 ; 0x08 638: 28 2f mov r18, r24 63a: 33 27 eor r19, r19 63c: ce 01 movw r24, r28 63e: 01 96 adiw r24, 0x01 ; 1 640: 82 0f add r24, r18 642: 93 1f adc r25, r19 644: fc 01 movw r30, r24 646: 33 96 adiw r30, 0x03 ; 3 648: 80 81 ld r24, Z 64a: 80 93 2f 00 sts 0x002F, r24 64e: 80 91 2e 00 lds r24, 0x002E 652: 88 23 and r24, r24 654: 0c f0 brlt .+2 ; 0x658 656: fb cf rjmp .-10 ; 0x64e 658: 88 85 ldd r24, Y+8 ; 0x08 65a: 8f 5f subi r24, 0xFF ; 255 65c: 88 87 std Y+8, r24 ; 0x08 65e: e8 cf rjmp .-48 ; 0x630 660: 80 91 38 00 lds r24, 0x0038 664: 81 60 ori r24, 0x01 ; 1 666: 80 93 38 00 sts 0x0038, r24 ENABLE_GLOBAL_INT(); 66a: 78 94 sei 66c: 28 96 adiw r28, 0x08 ; 8 66e: 0f b6 in r0, 0x3f ; 63 670: f8 94 cli 672: de bf out 0x3e, r29 ; 62 674: 0f be out 0x3f, r0 ; 63 676: cd bf out 0x3d, r28 ; 61 678: df 91 pop r29 67a: cf 91 pop r28 67c: 08 95 ret 0000067e : // RETURN VALUE: // BOOL // Successful transmission (acknowledgment received) //------------------------------------------------------------------------------------------------------- BOOL basicRfSendPacket(BASIC_RF_TX_INFO *pRTI) { 67e: cf 93 push r28 680: df 93 push r29 682: cd b7 in r28, 0x3d ; 61 684: de b7 in r29, 0x3e ; 62 686: 2a 97 sbiw r28, 0x0a ; 10 688: 0f b6 in r0, 0x3f ; 63 68a: f8 94 cli 68c: de bf out 0x3e, r29 ; 62 68e: 0f be out 0x3f, r0 ; 63 690: cd bf out 0x3d, r28 ; 61 692: 9a 83 std Y+2, r25 ; 0x02 694: 89 83 std Y+1, r24 ; 0x01 WORD frameControlField; UINT8 packetLength; BOOL success; BYTE spiStatusByte; // Wait until the transceiver is idle while (FIFOP_IS_1 || SFD_IS_1); 696: 80 91 30 00 lds r24, 0x0030 69a: 99 27 eor r25, r25 69c: 81 70 andi r24, 0x01 ; 1 69e: 90 70 andi r25, 0x00 ; 0 6a0: 00 97 sbiw r24, 0x00 ; 0 6a2: c9 f7 brne .-14 ; 0x696 6a4: 80 91 30 00 lds r24, 0x0030 6a8: 99 27 eor r25, r25 6aa: 80 71 andi r24, 0x10 ; 16 6ac: 90 70 andi r25, 0x00 ; 0 6ae: 00 97 sbiw r24, 0x00 ; 0 6b0: 91 f7 brne .-28 ; 0x696 // Turn off global interrupts to avoid interference on the SPI interface DISABLE_GLOBAL_INT(); 6b2: f8 94 cli // Flush the TX FIFO just in case... FASTSPI_STROBE(CC2420_SFLUSHTX); 6b4: 80 91 38 00 lds r24, 0x0038 6b8: 8e 7f andi r24, 0xFE ; 254 6ba: 80 93 38 00 sts 0x0038, r24 6be: 89 e0 ldi r24, 0x09 ; 9 6c0: 80 93 2f 00 sts 0x002F, r24 6c4: 80 91 2e 00 lds r24, 0x002E 6c8: 88 23 and r24, r24 6ca: 0c f0 brlt .+2 ; 0x6ce 6cc: fb cf rjmp .-10 ; 0x6c4 6ce: 80 91 38 00 lds r24, 0x0038 6d2: 81 60 ori r24, 0x01 ; 1 6d4: 80 93 38 00 sts 0x0038, r24 // Turn on RX if necessary if (!rfSettings.receiveOn) FASTSPI_STROBE(CC2420_SRXON); 6d8: 80 91 02 02 lds r24, 0x0202 6dc: 88 23 and r24, r24 6de: 91 f4 brne .+36 ; 0x704 6e0: 80 91 38 00 lds r24, 0x0038 6e4: 8e 7f andi r24, 0xFE ; 254 6e6: 80 93 38 00 sts 0x0038, r24 6ea: 83 e0 ldi r24, 0x03 ; 3 6ec: 80 93 2f 00 sts 0x002F, r24 6f0: 80 91 2e 00 lds r24, 0x002E 6f4: 88 23 and r24, r24 6f6: 0c f0 brlt .+2 ; 0x6fa 6f8: fb cf rjmp .-10 ; 0x6f0 6fa: 80 91 38 00 lds r24, 0x0038 6fe: 81 60 ori r24, 0x01 ; 1 700: 80 93 38 00 sts 0x0038, r24 // Wait for the RSSI value to become valid do { FASTSPI_UPD_STATUS(spiStatusByte); 704: 80 91 38 00 lds r24, 0x0038 708: 8e 7f andi r24, 0xFE ; 254 70a: 80 93 38 00 sts 0x0038, r24 70e: 10 92 2f 00 sts 0x002F, r1 712: 80 91 2e 00 lds r24, 0x002E 716: 88 23 and r24, r24 718: 0c f0 brlt .+2 ; 0x71c 71a: fb cf rjmp .-10 ; 0x712 71c: 80 91 2f 00 lds r24, 0x002F 720: 8f 83 std Y+7, r24 ; 0x07 722: 80 91 38 00 lds r24, 0x0038 726: 81 60 ori r24, 0x01 ; 1 728: 80 93 38 00 sts 0x0038, r24 } while (!(spiStatusByte & BM(CC2420_RSSI_VALID))); 72c: 8f 81 ldd r24, Y+7 ; 0x07 72e: 99 27 eor r25, r25 730: 82 70 andi r24, 0x02 ; 2 732: 90 70 andi r25, 0x00 ; 0 734: 00 97 sbiw r24, 0x00 ; 0 736: 09 f4 brne .+2 ; 0x73a 738: e5 cf rjmp .-54 ; 0x704 // TX begins after the CCA check has passed do { FASTSPI_STROBE(CC2420_STXONCCA); 73a: 80 91 38 00 lds r24, 0x0038 73e: 8e 7f andi r24, 0xFE ; 254 740: 80 93 38 00 sts 0x0038, r24 744: 85 e0 ldi r24, 0x05 ; 5 746: 80 93 2f 00 sts 0x002F, r24 74a: 80 91 2e 00 lds r24, 0x002E 74e: 88 23 and r24, r24 750: 0c f0 brlt .+2 ; 0x754 752: fb cf rjmp .-10 ; 0x74a 754: 80 91 38 00 lds r24, 0x0038 758: 81 60 ori r24, 0x01 ; 1 75a: 80 93 38 00 sts 0x0038, r24 FASTSPI_UPD_STATUS(spiStatusByte); 75e: 80 91 38 00 lds r24, 0x0038 762: 8e 7f andi r24, 0xFE ; 254 764: 80 93 38 00 sts 0x0038, r24 768: 10 92 2f 00 sts 0x002F, r1 76c: 80 91 2e 00 lds r24, 0x002E 770: 88 23 and r24, r24 772: 0c f0 brlt .+2 ; 0x776 774: fb cf rjmp .-10 ; 0x76c 776: 80 91 2f 00 lds r24, 0x002F 77a: 8f 83 std Y+7, r24 ; 0x07 77c: 80 91 38 00 lds r24, 0x0038 780: 81 60 ori r24, 0x01 ; 1 782: 80 93 38 00 sts 0x0038, r24 halWait(100); 786: 84 e6 ldi r24, 0x64 ; 100 788: 90 e0 ldi r25, 0x00 ; 0 78a: 0e 94 3a 01 call 0x274 } while (!(spiStatusByte & BM(CC2420_TX_ACTIVE))); 78e: 8f 81 ldd r24, Y+7 ; 0x07 790: 99 27 eor r25, r25 792: 88 70 andi r24, 0x08 ; 8 794: 90 70 andi r25, 0x00 ; 0 796: 00 97 sbiw r24, 0x00 ; 0 798: 09 f4 brne .+2 ; 0x79c 79a: cf cf rjmp .-98 ; 0x73a // Write the packet to the TX FIFO (the FCS is appended automatically when AUTOCRC is enabled) packetLength = pRTI->length + BASIC_RF_PACKET_OVERHEAD_SIZE; 79c: e9 81 ldd r30, Y+1 ; 0x01 79e: fa 81 ldd r31, Y+2 ; 0x02 7a0: 84 81 ldd r24, Z+4 ; 0x04 7a2: 85 5f subi r24, 0xF5 ; 245 7a4: 8d 83 std Y+5, r24 ; 0x05 FASTSPI_WRITE_FIFO((BYTE*)&packetLength, 1); // Packet length 7a6: 80 91 38 00 lds r24, 0x0038 7aa: 8e 7f andi r24, 0xFE ; 254 7ac: 80 93 38 00 sts 0x0038, r24 7b0: 8e e3 ldi r24, 0x3E ; 62 7b2: 80 93 2f 00 sts 0x002F, r24 7b6: 80 91 2e 00 lds r24, 0x002E 7ba: 88 23 and r24, r24 7bc: 0c f0 brlt .+2 ; 0x7c0 7be: fb cf rjmp .-10 ; 0x7b6 7c0: 18 86 std Y+8, r1 ; 0x08 7c2: 88 85 ldd r24, Y+8 ; 0x08 7c4: 88 23 and r24, r24 7c6: a9 f4 brne .+42 ; 0x7f2 7c8: 88 85 ldd r24, Y+8 ; 0x08 7ca: 28 2f mov r18, r24 7cc: 33 27 eor r19, r19 7ce: ce 01 movw r24, r28 7d0: 01 96 adiw r24, 0x01 ; 1 7d2: 82 0f add r24, r18 7d4: 93 1f adc r25, r19 7d6: fc 01 movw r30, r24 7d8: 34 96 adiw r30, 0x04 ; 4 7da: 80 81 ld r24, Z 7dc: 80 93 2f 00 sts 0x002F, r24 7e0: 80 91 2e 00 lds r24, 0x002E 7e4: 88 23 and r24, r24 7e6: 0c f0 brlt .+2 ; 0x7ea 7e8: fb cf rjmp .-10 ; 0x7e0 7ea: 88 85 ldd r24, Y+8 ; 0x08 7ec: 8f 5f subi r24, 0xFF ; 255 7ee: 88 87 std Y+8, r24 ; 0x08 7f0: e8 cf rjmp .-48 ; 0x7c2 7f2: 80 91 38 00 lds r24, 0x0038 7f6: 81 60 ori r24, 0x01 ; 1 7f8: 80 93 38 00 sts 0x0038, r24 frameControlField = pRTI->ackRequest ? BASIC_RF_FCF_ACK : BASIC_RF_FCF_NOACK; 7fc: e9 81 ldd r30, Y+1 ; 0x01 7fe: fa 81 ldd r31, Y+2 ; 0x02 800: 87 81 ldd r24, Z+7 ; 0x07 802: 88 23 and r24, r24 804: 29 f0 breq .+10 ; 0x810 806: 81 e6 ldi r24, 0x61 ; 97 808: 98 e8 ldi r25, 0x88 ; 136 80a: 9a 87 std Y+10, r25 ; 0x0a 80c: 89 87 std Y+9, r24 ; 0x09 80e: 04 c0 rjmp .+8 ; 0x818 810: 81 e4 ldi r24, 0x41 ; 65 812: 98 e8 ldi r25, 0x88 ; 136 814: 9a 87 std Y+10, r25 ; 0x0a 816: 89 87 std Y+9, r24 ; 0x09 818: 89 85 ldd r24, Y+9 ; 0x09 81a: 9a 85 ldd r25, Y+10 ; 0x0a 81c: 9c 83 std Y+4, r25 ; 0x04 81e: 8b 83 std Y+3, r24 ; 0x03 FASTSPI_WRITE_FIFO((BYTE*) &frameControlField, 2); // Frame control field 820: 80 91 38 00 lds r24, 0x0038 824: 8e 7f andi r24, 0xFE ; 254 826: 80 93 38 00 sts 0x0038, r24 82a: 8e e3 ldi r24, 0x3E ; 62 82c: 80 93 2f 00 sts 0x002F, r24 830: 80 91 2e 00 lds r24, 0x002E 834: 88 23 and r24, r24 836: 0c f0 brlt .+2 ; 0x83a 838: fb cf rjmp .-10 ; 0x830 83a: 18 86 std Y+8, r1 ; 0x08 83c: 88 85 ldd r24, Y+8 ; 0x08 83e: 82 30 cpi r24, 0x02 ; 2 840: a8 f4 brcc .+42 ; 0x86c 842: 88 85 ldd r24, Y+8 ; 0x08 844: 28 2f mov r18, r24 846: 33 27 eor r19, r19 848: ce 01 movw r24, r28 84a: 01 96 adiw r24, 0x01 ; 1 84c: 82 0f add r24, r18 84e: 93 1f adc r25, r19 850: fc 01 movw r30, r24 852: 32 96 adiw r30, 0x02 ; 2 854: 80 81 ld r24, Z 856: 80 93 2f 00 sts 0x002F, r24 85a: 80 91 2e 00 lds r24, 0x002E 85e: 88 23 and r24, r24 860: 0c f0 brlt .+2 ; 0x864 862: fb cf rjmp .-10 ; 0x85a 864: 88 85 ldd r24, Y+8 ; 0x08 866: 8f 5f subi r24, 0xFF ; 255 868: 88 87 std Y+8, r24 ; 0x08 86a: e8 cf rjmp .-48 ; 0x83c 86c: 80 91 38 00 lds r24, 0x0038 870: 81 60 ori r24, 0x01 ; 1 872: 80 93 38 00 sts 0x0038, r24 FASTSPI_WRITE_FIFO((BYTE*) &rfSettings.txSeqNumber, 1); // Sequence number 876: 80 91 38 00 lds r24, 0x0038 87a: 8e 7f andi r24, 0xFE ; 254 87c: 80 93 38 00 sts 0x0038, r24 880: 8e e3 ldi r24, 0x3E ; 62 882: 80 93 2f 00 sts 0x002F, r24 886: 80 91 2e 00 lds r24, 0x002E 88a: 88 23 and r24, r24 88c: 0c f0 brlt .+2 ; 0x890 88e: fb cf rjmp .-10 ; 0x886 890: 18 86 std Y+8, r1 ; 0x08 892: 88 85 ldd r24, Y+8 ; 0x08 894: 88 23 and r24, r24 896: 89 f4 brne .+34 ; 0x8ba 898: 88 85 ldd r24, Y+8 ; 0x08 89a: 99 27 eor r25, r25 89c: fc 01 movw r30, r24 89e: e4 50 subi r30, 0x04 ; 4 8a0: fe 4f sbci r31, 0xFE ; 254 8a2: 80 81 ld r24, Z 8a4: 80 93 2f 00 sts 0x002F, r24 8a8: 80 91 2e 00 lds r24, 0x002E 8ac: 88 23 and r24, r24 8ae: 0c f0 brlt .+2 ; 0x8b2 8b0: fb cf rjmp .-10 ; 0x8a8 8b2: 88 85 ldd r24, Y+8 ; 0x08 8b4: 8f 5f subi r24, 0xFF ; 255 8b6: 88 87 std Y+8, r24 ; 0x08 8b8: ec cf rjmp .-40 ; 0x892 8ba: 80 91 38 00 lds r24, 0x0038 8be: 81 60 ori r24, 0x01 ; 1 8c0: 80 93 38 00 sts 0x0038, r24 FASTSPI_WRITE_FIFO((BYTE*) &rfSettings.panId, 2); // Dest. PAN ID 8c4: 80 91 38 00 lds r24, 0x0038 8c8: 8e 7f andi r24, 0xFE ; 254 8ca: 80 93 38 00 sts 0x0038, r24 8ce: 8e e3 ldi r24, 0x3E ; 62 8d0: 80 93 2f 00 sts 0x002F, r24 8d4: 80 91 2e 00 lds r24, 0x002E 8d8: 88 23 and r24, r24 8da: 0c f0 brlt .+2 ; 0x8de 8dc: fb cf rjmp .-10 ; 0x8d4 8de: 18 86 std Y+8, r1 ; 0x08 8e0: 88 85 ldd r24, Y+8 ; 0x08 8e2: 82 30 cpi r24, 0x02 ; 2 8e4: 88 f4 brcc .+34 ; 0x908 8e6: 88 85 ldd r24, Y+8 ; 0x08 8e8: 99 27 eor r25, r25 8ea: fc 01 movw r30, r24 8ec: e2 50 subi r30, 0x02 ; 2 8ee: fe 4f sbci r31, 0xFE ; 254 8f0: 80 81 ld r24, Z 8f2: 80 93 2f 00 sts 0x002F, r24 8f6: 80 91 2e 00 lds r24, 0x002E 8fa: 88 23 and r24, r24 8fc: 0c f0 brlt .+2 ; 0x900 8fe: fb cf rjmp .-10 ; 0x8f6 900: 88 85 ldd r24, Y+8 ; 0x08 902: 8f 5f subi r24, 0xFF ; 255 904: 88 87 std Y+8, r24 ; 0x08 906: ec cf rjmp .-40 ; 0x8e0 908: 80 91 38 00 lds r24, 0x0038 90c: 81 60 ori r24, 0x01 ; 1 90e: 80 93 38 00 sts 0x0038, r24 FASTSPI_WRITE_FIFO((BYTE*) &pRTI->destAddr, 2); // Dest. address 912: 80 91 38 00 lds r24, 0x0038 916: 8e 7f andi r24, 0xFE ; 254 918: 80 93 38 00 sts 0x0038, r24 91c: 8e e3 ldi r24, 0x3E ; 62 91e: 80 93 2f 00 sts 0x002F, r24 922: 80 91 2e 00 lds r24, 0x002E 926: 88 23 and r24, r24 928: 0c f0 brlt .+2 ; 0x92c 92a: fb cf rjmp .-10 ; 0x922 92c: 18 86 std Y+8, r1 ; 0x08 92e: 88 85 ldd r24, Y+8 ; 0x08 930: 82 30 cpi r24, 0x02 ; 2 932: a8 f4 brcc .+42 ; 0x95e 934: 88 85 ldd r24, Y+8 ; 0x08 936: 28 2f mov r18, r24 938: 33 27 eor r19, r19 93a: 89 81 ldd r24, Y+1 ; 0x01 93c: 9a 81 ldd r25, Y+2 ; 0x02 93e: 82 0f add r24, r18 940: 93 1f adc r25, r19 942: fc 01 movw r30, r24 944: 32 96 adiw r30, 0x02 ; 2 946: 80 81 ld r24, Z 948: 80 93 2f 00 sts 0x002F, r24 94c: 80 91 2e 00 lds r24, 0x002E 950: 88 23 and r24, r24 952: 0c f0 brlt .+2 ; 0x956 954: fb cf rjmp .-10 ; 0x94c 956: 88 85 ldd r24, Y+8 ; 0x08 958: 8f 5f subi r24, 0xFF ; 255 95a: 88 87 std Y+8, r24 ; 0x08 95c: e8 cf rjmp .-48 ; 0x92e 95e: 80 91 38 00 lds r24, 0x0038 962: 81 60 ori r24, 0x01 ; 1 964: 80 93 38 00 sts 0x0038, r24 FASTSPI_WRITE_FIFO((BYTE*) &rfSettings.myAddr, 2); // Source address 968: 80 91 38 00 lds r24, 0x0038 96c: 8e 7f andi r24, 0xFE ; 254 96e: 80 93 38 00 sts 0x0038, r24 972: 8e e3 ldi r24, 0x3E ; 62 974: 80 93 2f 00 sts 0x002F, r24 978: 80 91 2e 00 lds r24, 0x002E 97c: 88 23 and r24, r24 97e: 0c f0 brlt .+2 ; 0x982 980: fb cf rjmp .-10 ; 0x978 982: 18 86 std Y+8, r1 ; 0x08 984: 88 85 ldd r24, Y+8 ; 0x08 986: 82 30 cpi r24, 0x02 ; 2 988: 88 f4 brcc .+34 ; 0x9ac 98a: 88 85 ldd r24, Y+8 ; 0x08 98c: 99 27 eor r25, r25 98e: fc 01 movw r30, r24 990: e0 50 subi r30, 0x00 ; 0 992: fe 4f sbci r31, 0xFE ; 254 994: 80 81 ld r24, Z 996: 80 93 2f 00 sts 0x002F, r24 99a: 80 91 2e 00 lds r24, 0x002E 99e: 88 23 and r24, r24 9a0: 0c f0 brlt .+2 ; 0x9a4 9a2: fb cf rjmp .-10 ; 0x99a 9a4: 88 85 ldd r24, Y+8 ; 0x08 9a6: 8f 5f subi r24, 0xFF ; 255 9a8: 88 87 std Y+8, r24 ; 0x08 9aa: ec cf rjmp .-40 ; 0x984 9ac: 80 91 38 00 lds r24, 0x0038 9b0: 81 60 ori r24, 0x01 ; 1 9b2: 80 93 38 00 sts 0x0038, r24 FASTSPI_WRITE_FIFO((BYTE*) pRTI->pPayload, pRTI->length); // Payload 9b6: 80 91 38 00 lds r24, 0x0038 9ba: 8e 7f andi r24, 0xFE ; 254 9bc: 80 93 38 00 sts 0x0038, r24 9c0: 8e e3 ldi r24, 0x3E ; 62 9c2: 80 93 2f 00 sts 0x002F, r24 9c6: 80 91 2e 00 lds r24, 0x002E 9ca: 88 23 and r24, r24 9cc: 0c f0 brlt .+2 ; 0x9d0 9ce: fb cf rjmp .-10 ; 0x9c6 9d0: 18 86 std Y+8, r1 ; 0x08 9d2: 88 85 ldd r24, Y+8 ; 0x08 9d4: 28 2f mov r18, r24 9d6: 33 27 eor r19, r19 9d8: e9 81 ldd r30, Y+1 ; 0x01 9da: fa 81 ldd r31, Y+2 ; 0x02 9dc: 84 81 ldd r24, Z+4 ; 0x04 9de: 99 27 eor r25, r25 9e0: 87 fd sbrc r24, 7 9e2: 90 95 com r25 9e4: 28 17 cp r18, r24 9e6: 39 07 cpc r19, r25 9e8: b4 f4 brge .+44 ; 0xa16 9ea: e9 81 ldd r30, Y+1 ; 0x01 9ec: fa 81 ldd r31, Y+2 ; 0x02 9ee: 88 85 ldd r24, Y+8 ; 0x08 9f0: 28 2f mov r18, r24 9f2: 33 27 eor r19, r19 9f4: 85 81 ldd r24, Z+5 ; 0x05 9f6: 96 81 ldd r25, Z+6 ; 0x06 9f8: f9 01 movw r30, r18 9fa: e8 0f add r30, r24 9fc: f9 1f adc r31, r25 9fe: 80 81 ld r24, Z a00: 80 93 2f 00 sts 0x002F, r24 a04: 80 91 2e 00 lds r24, 0x002E a08: 88 23 and r24, r24 a0a: 0c f0 brlt .+2 ; 0xa0e a0c: fb cf rjmp .-10 ; 0xa04 a0e: 88 85 ldd r24, Y+8 ; 0x08 a10: 8f 5f subi r24, 0xFF ; 255 a12: 88 87 std Y+8, r24 ; 0x08 a14: de cf rjmp .-68 ; 0x9d2 a16: 80 91 38 00 lds r24, 0x0038 a1a: 81 60 ori r24, 0x01 ; 1 a1c: 80 93 38 00 sts 0x0038, r24 // Wait for the transmission to begin before exiting (makes sure that this function cannot be called // a second time, and thereby cancelling the first transmission (observe the FIFOP + SFD test above). while (!SFD_IS_1); a20: 80 91 30 00 lds r24, 0x0030 a24: 99 27 eor r25, r25 a26: 80 71 andi r24, 0x10 ; 16 a28: 90 70 andi r25, 0x00 ; 0 a2a: 00 97 sbiw r24, 0x00 ; 0 a2c: 09 f4 brne .+2 ; 0xa30 a2e: f8 cf rjmp .-16 ; 0xa20 success = TRUE; a30: 81 e0 ldi r24, 0x01 ; 1 a32: 8e 83 std Y+6, r24 ; 0x06 // Turn interrupts back on ENABLE_GLOBAL_INT(); a34: 78 94 sei // Wait for the acknowledge to be received, if any if (pRTI->ackRequest) { a36: e9 81 ldd r30, Y+1 ; 0x01 a38: fa 81 ldd r31, Y+2 ; 0x02 a3a: 87 81 ldd r24, Z+7 ; 0x07 a3c: 88 23 and r24, r24 a3e: 89 f0 breq .+34 ; 0xa62 rfSettings.ackReceived = FALSE; a40: 10 92 fd 01 sts 0x01FD, r1 // Wait for the SFD to go low again while (SFD_IS_1); a44: 80 91 30 00 lds r24, 0x0030 a48: 99 27 eor r25, r25 a4a: 80 71 andi r24, 0x10 ; 16 a4c: 90 70 andi r25, 0x00 ; 0 a4e: 00 97 sbiw r24, 0x00 ; 0 a50: 09 f0 breq .+2 ; 0xa54 a52: f8 cf rjmp .-16 ; 0xa44 // We'll enter RX automatically, so just wait until we can be sure that the ack reception should have finished // The timeout consists of a 12-symbol turnaround time, the ack packet duration, and a small margin halWait((12 * BASIC_RF_SYMBOL_DURATION) + (BASIC_RF_ACK_DURATION) + (2 * BASIC_RF_SYMBOL_DURATION) + 100); a54: 84 ea ldi r24, 0xA4 ; 164 a56: 92 e0 ldi r25, 0x02 ; 2 a58: 0e 94 3a 01 call 0x274 // If an acknowledgment has been received (by the FIFOP interrupt), the ackReceived flag should be set success = rfSettings.ackReceived; a5c: 80 91 fd 01 lds r24, 0x01FD a60: 8e 83 std Y+6, r24 ; 0x06 } // Turn off the receiver if it should not continue to be enabled DISABLE_GLOBAL_INT(); a62: f8 94 cli if (!rfSettings.receiveOn) FASTSPI_STROBE(CC2420_SRFOFF); a64: 80 91 02 02 lds r24, 0x0202 a68: 88 23 and r24, r24 a6a: 91 f4 brne .+36 ; 0xa90 a6c: 80 91 38 00 lds r24, 0x0038 a70: 8e 7f andi r24, 0xFE ; 254 a72: 80 93 38 00 sts 0x0038, r24 a76: 86 e0 ldi r24, 0x06 ; 6 a78: 80 93 2f 00 sts 0x002F, r24 a7c: 80 91 2e 00 lds r24, 0x002E a80: 88 23 and r24, r24 a82: 0c f0 brlt .+2 ; 0xa86 a84: fb cf rjmp .-10 ; 0xa7c a86: 80 91 38 00 lds r24, 0x0038 a8a: 81 60 ori r24, 0x01 ; 1 a8c: 80 93 38 00 sts 0x0038, r24 ENABLE_GLOBAL_INT(); a90: 78 94 sei // Increment the sequence number, and return the result rfSettings.txSeqNumber++; a92: 80 91 fc 01 lds r24, 0x01FC a96: 8f 5f subi r24, 0xFF ; 255 a98: 80 93 fc 01 sts 0x01FC, r24 return success; a9c: 8e 81 ldd r24, Y+6 ; 0x06 a9e: 99 27 eor r25, r25 aa0: 2a 96 adiw r28, 0x0a ; 10 aa2: 0f b6 in r0, 0x3f ; 63 aa4: f8 94 cli aa6: de bf out 0x3e, r29 ; 62 aa8: 0f be out 0x3f, r0 ; 63 aaa: cd bf out 0x3d, r28 ; 61 aac: df 91 pop r29 aae: cf 91 pop r28 ab0: 08 95 ret 00000ab2 : // DESCRIPTION: // Enables the CC2420 receiver and the FIFOP interrupt. When a packet is received through this // interrupt, it will call halRfReceivePacket(...), which must be defined by the application //------------------------------------------------------------------------------------------------------- void basicRfReceiveOn(void) { ab2: cf 93 push r28 ab4: df 93 push r29 ab6: cd b7 in r28, 0x3d ; 61 ab8: de b7 in r29, 0x3e ; 62 rfSettings.receiveOn = TRUE; aba: 81 e0 ldi r24, 0x01 ; 1 abc: 80 93 02 02 sts 0x0202, r24 FASTSPI_STROBE(CC2420_SRXON); ac0: 80 91 38 00 lds r24, 0x0038 ac4: 8e 7f andi r24, 0xFE ; 254 ac6: 80 93 38 00 sts 0x0038, r24 aca: 83 e0 ldi r24, 0x03 ; 3 acc: 80 93 2f 00 sts 0x002F, r24 ad0: 80 91 2e 00 lds r24, 0x002E ad4: 88 23 and r24, r24 ad6: 0c f0 brlt .+2 ; 0xada ad8: fb cf rjmp .-10 ; 0xad0 ada: 80 91 38 00 lds r24, 0x0038 ade: 81 60 ori r24, 0x01 ; 1 ae0: 80 93 38 00 sts 0x0038, r24 FASTSPI_STROBE(CC2420_SFLUSHRX); ae4: 80 91 38 00 lds r24, 0x0038 ae8: 8e 7f andi r24, 0xFE ; 254 aea: 80 93 38 00 sts 0x0038, r24 aee: 88 e0 ldi r24, 0x08 ; 8 af0: 80 93 2f 00 sts 0x002F, r24 af4: 80 91 2e 00 lds r24, 0x002E af8: 88 23 and r24, r24 afa: 0c f0 brlt .+2 ; 0xafe afc: fb cf rjmp .-10 ; 0xaf4 afe: 80 91 38 00 lds r24, 0x0038 b02: 81 60 ori r24, 0x01 ; 1 b04: 80 93 38 00 sts 0x0038, r24 b08: df 91 pop r29 b0a: cf 91 pop r28 b0c: 08 95 ret 00000b0e : //ENABLE_FIFOP_INT(); } // basicRfReceiveOn //------------------------------------------------------------------------------------------------------- // void halRfReceiveOff(void) // // DESCRIPTION: // Disables the CC2420 receiver and the FIFOP interrupt. //------------------------------------------------------------------------------------------------------- void basicRfReceiveOff(void) { b0e: cf 93 push r28 b10: df 93 push r29 b12: cd b7 in r28, 0x3d ; 61 b14: de b7 in r29, 0x3e ; 62 rfSettings.receiveOn = FALSE; b16: 10 92 02 02 sts 0x0202, r1 FASTSPI_STROBE(CC2420_SRFOFF); b1a: 80 91 38 00 lds r24, 0x0038 b1e: 8e 7f andi r24, 0xFE ; 254 b20: 80 93 38 00 sts 0x0038, r24 b24: 86 e0 ldi r24, 0x06 ; 6 b26: 80 93 2f 00 sts 0x002F, r24 b2a: 80 91 2e 00 lds r24, 0x002E b2e: 88 23 and r24, r24 b30: 0c f0 brlt .+2 ; 0xb34 b32: fb cf rjmp .-10 ; 0xb2a b34: 80 91 38 00 lds r24, 0x0038 b38: 81 60 ori r24, 0x01 ; 1 b3a: 80 93 38 00 sts 0x0038, r24 DISABLE_FIFOP_INT(); b3e: 80 91 59 00 lds r24, 0x0059 b42: 8e 7f andi r24, 0xFE ; 254 b44: 80 93 59 00 sts 0x0059, r24 b48: df 91 pop r29 b4a: cf 91 pop r28 b4c: 08 95 ret 00000b4e <__vector_1>: } // basicRfReceiveOff //------------------------------------------------------------------------------------------------------- // SIGNAL(SIG_INTERRUPT0) - CC2420 FIFOP interrupt service routine // // DESCRIPTION: // When a packet has been completely received, this ISR will extract the data from the RX FIFO, put // it into the active BASIC_RF_RX_INFO structure, and call basicRfReceivePacket() (defined by the // application). FIFO overflow and illegally formatted packets is handled by this routine. // // Note: Packets are acknowledged automatically by CC2420 through the auto-acknowledgment feature. //------------------------------------------------------------------------------------------------------- SIGNAL(SIG_INTERRUPT0) { b4e: 1f 92 push r1 b50: 0f 92 push r0 b52: 0f b6 in r0, 0x3f ; 63 b54: 0f 92 push r0 b56: 11 24 eor r1, r1 b58: 2f 93 push r18 b5a: 3f 93 push r19 b5c: 4f 93 push r20 b5e: 5f 93 push r21 b60: 6f 93 push r22 b62: 7f 93 push r23 b64: 8f 93 push r24 b66: 9f 93 push r25 b68: af 93 push r26 b6a: bf 93 push r27 b6c: ef 93 push r30 b6e: ff 93 push r31 b70: cf 93 push r28 b72: df 93 push r29 b74: cd b7 in r28, 0x3d ; 61 b76: de b7 in r29, 0x3e ; 62 b78: 26 97 sbiw r28, 0x06 ; 6 b7a: de bf out 0x3e, r29 ; 62 b7c: cd bf out 0x3d, r28 ; 61 WORD frameControlField; INT8 length; BYTE pFooter[2]; // Clean up and exit in case of FIFO overflow, which is indicated by FIFOP = 1 and FIFO = 0 if((FIFOP_IS_1) && (!(FIFO_IS_1))) b7e: 80 91 30 00 lds r24, 0x0030 b82: 99 27 eor r25, r25 b84: 81 70 andi r24, 0x01 ; 1 b86: 90 70 andi r25, 0x00 ; 0 b88: 00 97 sbiw r24, 0x00 ; 0 b8a: 61 f1 breq .+88 ; 0xbe4 <__vector_1+0x96> b8c: 80 91 30 00 lds r24, 0x0030 b90: 99 27 eor r25, r25 b92: 82 70 andi r24, 0x02 ; 2 b94: 90 70 andi r25, 0x00 ; 0 b96: 00 97 sbiw r24, 0x00 ; 0 b98: 29 f5 brne .+74 ; 0xbe4 <__vector_1+0x96> { FASTSPI_STROBE(CC2420_SFLUSHRX); b9a: 80 91 38 00 lds r24, 0x0038 b9e: 8e 7f andi r24, 0xFE ; 254 ba0: 80 93 38 00 sts 0x0038, r24 ba4: 88 e0 ldi r24, 0x08 ; 8 ba6: 80 93 2f 00 sts 0x002F, r24 baa: 80 91 2e 00 lds r24, 0x002E bae: 88 23 and r24, r24 bb0: 0c f0 brlt .+2 ; 0xbb4 <__vector_1+0x66> bb2: fb cf rjmp .-10 ; 0xbaa <__vector_1+0x5c> bb4: 80 91 38 00 lds r24, 0x0038 bb8: 81 60 ori r24, 0x01 ; 1 bba: 80 93 38 00 sts 0x0038, r24 FASTSPI_STROBE(CC2420_SFLUSHRX); bbe: 80 91 38 00 lds r24, 0x0038 bc2: 8e 7f andi r24, 0xFE ; 254 bc4: 80 93 38 00 sts 0x0038, r24 bc8: 88 e0 ldi r24, 0x08 ; 8 bca: 80 93 2f 00 sts 0x002F, r24 bce: 80 91 2e 00 lds r24, 0x002E bd2: 88 23 and r24, r24 bd4: 0c f0 brlt .+2 ; 0xbd8 <__vector_1+0x8a> bd6: fb cf rjmp .-10 ; 0xbce <__vector_1+0x80> bd8: 80 91 38 00 lds r24, 0x0038 bdc: 81 60 ori r24, 0x01 ; 1 bde: 80 93 38 00 sts 0x0038, r24 return; be2: 18 c2 rjmp .+1072 ; 0x1014 <__vector_1+0x4c6> } // Payload length FASTSPI_READ_FIFO_BYTE(length); be4: 80 91 38 00 lds r24, 0x0038 be8: 8e 7f andi r24, 0xFE ; 254 bea: 80 93 38 00 sts 0x0038, r24 bee: 8f e7 ldi r24, 0x7F ; 127 bf0: 80 93 2f 00 sts 0x002F, r24 bf4: 80 91 2e 00 lds r24, 0x002E bf8: 88 23 and r24, r24 bfa: 0c f0 brlt .+2 ; 0xbfe <__vector_1+0xb0> bfc: fb cf rjmp .-10 ; 0xbf4 <__vector_1+0xa6> bfe: 10 92 2f 00 sts 0x002F, r1 c02: 80 91 2e 00 lds r24, 0x002E c06: 88 23 and r24, r24 c08: 0c f0 brlt .+2 ; 0xc0c <__vector_1+0xbe> c0a: fb cf rjmp .-10 ; 0xc02 <__vector_1+0xb4> c0c: 80 91 2f 00 lds r24, 0x002F c10: 8b 83 std Y+3, r24 ; 0x03 c12: 80 91 38 00 lds r24, 0x0038 c16: 81 60 ori r24, 0x01 ; 1 c18: 80 93 38 00 sts 0x0038, r24 length &= BASIC_RF_LENGTH_MASK; // Ignore MSB c1c: 8b 81 ldd r24, Y+3 ; 0x03 c1e: 8f 77 andi r24, 0x7F ; 127 c20: 8b 83 std Y+3, r24 ; 0x03 // Ignore the packet if the length is too short if (length < BASIC_RF_ACK_PACKET_SIZE) c22: 8b 81 ldd r24, Y+3 ; 0x03 c24: 85 30 cpi r24, 0x05 ; 5 c26: 84 f5 brge .+96 ; 0xc88 <__vector_1+0x13a> { FASTSPI_READ_FIFO_GARBAGE(length); c28: 80 91 38 00 lds r24, 0x0038 c2c: 8e 7f andi r24, 0xFE ; 254 c2e: 80 93 38 00 sts 0x0038, r24 c32: 8f e7 ldi r24, 0x7F ; 127 c34: 80 93 2f 00 sts 0x002F, r24 c38: 80 91 2e 00 lds r24, 0x002E c3c: 88 23 and r24, r24 c3e: 0c f0 brlt .+2 ; 0xc42 <__vector_1+0xf4> c40: fb cf rjmp .-10 ; 0xc38 <__vector_1+0xea> c42: 1e 82 std Y+6, r1 ; 0x06 c44: 8e 81 ldd r24, Y+6 ; 0x06 c46: 28 2f mov r18, r24 c48: 33 27 eor r19, r19 c4a: 8b 81 ldd r24, Y+3 ; 0x03 c4c: 99 27 eor r25, r25 c4e: 87 fd sbrc r24, 7 c50: 90 95 com r25 c52: 28 17 cp r18, r24 c54: 39 07 cpc r19, r25 c56: 94 f4 brge .+36 ; 0xc7c <__vector_1+0x12e> c58: 80 91 30 00 lds r24, 0x0030 c5c: 99 27 eor r25, r25 c5e: 82 70 andi r24, 0x02 ; 2 c60: 90 70 andi r25, 0x00 ; 0 c62: 00 97 sbiw r24, 0x00 ; 0 c64: 59 f0 breq .+22 ; 0xc7c <__vector_1+0x12e> c66: 10 92 2f 00 sts 0x002F, r1 c6a: 80 91 2e 00 lds r24, 0x002E c6e: 88 23 and r24, r24 c70: 0c f0 brlt .+2 ; 0xc74 <__vector_1+0x126> c72: fb cf rjmp .-10 ; 0xc6a <__vector_1+0x11c> c74: 8e 81 ldd r24, Y+6 ; 0x06 c76: 8f 5f subi r24, 0xFF ; 255 c78: 8e 83 std Y+6, r24 ; 0x06 c7a: e4 cf rjmp .-56 ; 0xc44 <__vector_1+0xf6> c7c: 80 91 38 00 lds r24, 0x0038 c80: 81 60 ori r24, 0x01 ; 1 c82: 80 93 38 00 sts 0x0038, r24 c86: c6 c1 rjmp .+908 ; 0x1014 <__vector_1+0x4c6> // Otherwise, if the length is valid, then proceed with the reset of the packet } else { // Register the payload length rfSettings.pRxInfo->length = length - BASIC_RF_PACKET_OVERHEAD_SIZE; c88: e0 91 fa 01 lds r30, 0x01FA c8c: f0 91 fb 01 lds r31, 0x01FB c90: 8b 81 ldd r24, Y+3 ; 0x03 c92: 8b 50 subi r24, 0x0B ; 11 c94: 85 83 std Z+5, r24 ; 0x05 // Read the frame control field and the data sequence number FASTSPI_READ_FIFO_NO_WAIT((BYTE*) &frameControlField, 2); c96: 80 91 38 00 lds r24, 0x0038 c9a: 8e 7f andi r24, 0xFE ; 254 c9c: 80 93 38 00 sts 0x0038, r24 ca0: 8f e7 ldi r24, 0x7F ; 127 ca2: 80 93 2f 00 sts 0x002F, r24 ca6: 80 91 2e 00 lds r24, 0x002E caa: 88 23 and r24, r24 cac: 0c f0 brlt .+2 ; 0xcb0 <__vector_1+0x162> cae: fb cf rjmp .-10 ; 0xca6 <__vector_1+0x158> cb0: 1e 82 std Y+6, r1 ; 0x06 cb2: 8e 81 ldd r24, Y+6 ; 0x06 cb4: 82 30 cpi r24, 0x02 ; 2 cb6: b0 f4 brcc .+44 ; 0xce4 <__vector_1+0x196> cb8: 10 92 2f 00 sts 0x002F, r1 cbc: 80 91 2e 00 lds r24, 0x002E cc0: 88 23 and r24, r24 cc2: 0c f0 brlt .+2 ; 0xcc6 <__vector_1+0x178> cc4: fb cf rjmp .-10 ; 0xcbc <__vector_1+0x16e> cc6: 8e 81 ldd r24, Y+6 ; 0x06 cc8: 28 2f mov r18, r24 cca: 33 27 eor r19, r19 ccc: ce 01 movw r24, r28 cce: 01 96 adiw r24, 0x01 ; 1 cd0: f9 01 movw r30, r18 cd2: e8 0f add r30, r24 cd4: f9 1f adc r31, r25 cd6: 80 91 2f 00 lds r24, 0x002F cda: 80 83 st Z, r24 cdc: 8e 81 ldd r24, Y+6 ; 0x06 cde: 8f 5f subi r24, 0xFF ; 255 ce0: 8e 83 std Y+6, r24 ; 0x06 ce2: e7 cf rjmp .-50 ; 0xcb2 <__vector_1+0x164> ce4: 80 91 38 00 lds r24, 0x0038 ce8: 81 60 ori r24, 0x01 ; 1 cea: 80 93 38 00 sts 0x0038, r24 rfSettings.pRxInfo->ackRequest = !!(frameControlField & BASIC_RF_FCF_ACK_BM); cee: e0 91 fa 01 lds r30, 0x01FA cf2: f0 91 fb 01 lds r31, 0x01FB cf6: 89 81 ldd r24, Y+1 ; 0x01 cf8: 9a 81 ldd r25, Y+2 ; 0x02 cfa: 96 95 lsr r25 cfc: 87 95 ror r24 cfe: 92 95 swap r25 d00: 82 95 swap r24 d02: 8f 70 andi r24, 0x0F ; 15 d04: 89 27 eor r24, r25 d06: 9f 70 andi r25, 0x0F ; 15 d08: 89 27 eor r24, r25 d0a: 81 70 andi r24, 0x01 ; 1 d0c: 80 87 std Z+8, r24 ; 0x08 FASTSPI_READ_FIFO_BYTE(rfSettings.pRxInfo->seqNumber); d0e: 80 91 38 00 lds r24, 0x0038 d12: 8e 7f andi r24, 0xFE ; 254 d14: 80 93 38 00 sts 0x0038, r24 d18: 8f e7 ldi r24, 0x7F ; 127 d1a: 80 93 2f 00 sts 0x002F, r24 d1e: 80 91 2e 00 lds r24, 0x002E d22: 88 23 and r24, r24 d24: 0c f0 brlt .+2 ; 0xd28 <__vector_1+0x1da> d26: fb cf rjmp .-10 ; 0xd1e <__vector_1+0x1d0> d28: 10 92 2f 00 sts 0x002F, r1 d2c: 80 91 2e 00 lds r24, 0x002E d30: 88 23 and r24, r24 d32: 0c f0 brlt .+2 ; 0xd36 <__vector_1+0x1e8> d34: fb cf rjmp .-10 ; 0xd2c <__vector_1+0x1de> d36: e0 91 fa 01 lds r30, 0x01FA d3a: f0 91 fb 01 lds r31, 0x01FB d3e: 80 91 2f 00 lds r24, 0x002F d42: 80 83 st Z, r24 d44: 80 91 38 00 lds r24, 0x0038 d48: 81 60 ori r24, 0x01 ; 1 d4a: 80 93 38 00 sts 0x0038, r24 // Is this an acknowledgment packet? if ((length == BASIC_RF_ACK_PACKET_SIZE) && (frameControlField == BASIC_RF_ACK_FCF) && (rfSettings.pRxInfo->seqNumber == rfSettings.txSeqNumber)) d4e: 8b 81 ldd r24, Y+3 ; 0x03 d50: 85 30 cpi r24, 0x05 ; 5 d52: 09 f0 breq .+2 ; 0xd56 <__vector_1+0x208> d54: 44 c0 rjmp .+136 ; 0xdde <__vector_1+0x290> d56: 89 81 ldd r24, Y+1 ; 0x01 d58: 9a 81 ldd r25, Y+2 ; 0x02 d5a: 82 30 cpi r24, 0x02 ; 2 d5c: 91 05 cpc r25, r1 d5e: 09 f0 breq .+2 ; 0xd62 <__vector_1+0x214> d60: 3e c0 rjmp .+124 ; 0xdde <__vector_1+0x290> d62: e0 91 fa 01 lds r30, 0x01FA d66: f0 91 fb 01 lds r31, 0x01FB d6a: 90 81 ld r25, Z d6c: 80 91 fc 01 lds r24, 0x01FC d70: 98 17 cp r25, r24 d72: a9 f5 brne .+106 ; 0xdde <__vector_1+0x290> { // Read the footer and check for CRC OK FASTSPI_READ_FIFO_NO_WAIT((BYTE*) pFooter, 2); d74: 80 91 38 00 lds r24, 0x0038 d78: 8e 7f andi r24, 0xFE ; 254 d7a: 80 93 38 00 sts 0x0038, r24 d7e: 8f e7 ldi r24, 0x7F ; 127 d80: 80 93 2f 00 sts 0x002F, r24 d84: 80 91 2e 00 lds r24, 0x002E d88: 88 23 and r24, r24 d8a: 0c f0 brlt .+2 ; 0xd8e <__vector_1+0x240> d8c: fb cf rjmp .-10 ; 0xd84 <__vector_1+0x236> d8e: 1e 82 std Y+6, r1 ; 0x06 d90: 8e 81 ldd r24, Y+6 ; 0x06 d92: 82 30 cpi r24, 0x02 ; 2 d94: b8 f4 brcc .+46 ; 0xdc4 <__vector_1+0x276> d96: 10 92 2f 00 sts 0x002F, r1 d9a: 80 91 2e 00 lds r24, 0x002E d9e: 88 23 and r24, r24 da0: 0c f0 brlt .+2 ; 0xda4 <__vector_1+0x256> da2: fb cf rjmp .-10 ; 0xd9a <__vector_1+0x24c> da4: 8e 81 ldd r24, Y+6 ; 0x06 da6: 28 2f mov r18, r24 da8: 33 27 eor r19, r19 daa: ce 01 movw r24, r28 dac: 01 96 adiw r24, 0x01 ; 1 dae: 82 0f add r24, r18 db0: 93 1f adc r25, r19 db2: fc 01 movw r30, r24 db4: 33 96 adiw r30, 0x03 ; 3 db6: 80 91 2f 00 lds r24, 0x002F dba: 80 83 st Z, r24 dbc: 8e 81 ldd r24, Y+6 ; 0x06 dbe: 8f 5f subi r24, 0xFF ; 255 dc0: 8e 83 std Y+6, r24 ; 0x06 dc2: e6 cf rjmp .-52 ; 0xd90 <__vector_1+0x242> dc4: 80 91 38 00 lds r24, 0x0038 dc8: 81 60 ori r24, 0x01 ; 1 dca: 80 93 38 00 sts 0x0038, r24 // Indicate the successful ack reception (this flag is polled by the transmission routine) if (pFooter[1] & BASIC_RF_CRC_OK_BM) rfSettings.ackReceived = TRUE; dce: 8d 81 ldd r24, Y+5 ; 0x05 dd0: 88 23 and r24, r24 dd2: 0c f0 brlt .+2 ; 0xdd6 <__vector_1+0x288> dd4: 1f c1 rjmp .+574 ; 0x1014 <__vector_1+0x4c6> dd6: 81 e0 ldi r24, 0x01 ; 1 dd8: 80 93 fd 01 sts 0x01FD, r24 ddc: 1b c1 rjmp .+566 ; 0x1014 <__vector_1+0x4c6> // Too small to be a valid packet? } else if (length < BASIC_RF_PACKET_OVERHEAD_SIZE) dde: 8b 81 ldd r24, Y+3 ; 0x03 de0: 8b 30 cpi r24, 0x0B ; 11 de2: 8c f5 brge .+98 ; 0xe46 <__vector_1+0x2f8> { FASTSPI_READ_FIFO_GARBAGE(length - 3); de4: 80 91 38 00 lds r24, 0x0038 de8: 8e 7f andi r24, 0xFE ; 254 dea: 80 93 38 00 sts 0x0038, r24 dee: 8f e7 ldi r24, 0x7F ; 127 df0: 80 93 2f 00 sts 0x002F, r24 df4: 80 91 2e 00 lds r24, 0x002E df8: 88 23 and r24, r24 dfa: 0c f0 brlt .+2 ; 0xdfe <__vector_1+0x2b0> dfc: fb cf rjmp .-10 ; 0xdf4 <__vector_1+0x2a6> dfe: 1e 82 std Y+6, r1 ; 0x06 e00: 8e 81 ldd r24, Y+6 ; 0x06 e02: 28 2f mov r18, r24 e04: 33 27 eor r19, r19 e06: 8b 81 ldd r24, Y+3 ; 0x03 e08: 99 27 eor r25, r25 e0a: 87 fd sbrc r24, 7 e0c: 90 95 com r25 e0e: 03 97 sbiw r24, 0x03 ; 3 e10: 28 17 cp r18, r24 e12: 39 07 cpc r19, r25 e14: 94 f4 brge .+36 ; 0xe3a <__vector_1+0x2ec> e16: 80 91 30 00 lds r24, 0x0030 e1a: 99 27 eor r25, r25 e1c: 82 70 andi r24, 0x02 ; 2 e1e: 90 70 andi r25, 0x00 ; 0 e20: 00 97 sbiw r24, 0x00 ; 0 e22: 59 f0 breq .+22 ; 0xe3a <__vector_1+0x2ec> e24: 10 92 2f 00 sts 0x002F, r1 e28: 80 91 2e 00 lds r24, 0x002E e2c: 88 23 and r24, r24 e2e: 0c f0 brlt .+2 ; 0xe32 <__vector_1+0x2e4> e30: fb cf rjmp .-10 ; 0xe28 <__vector_1+0x2da> e32: 8e 81 ldd r24, Y+6 ; 0x06 e34: 8f 5f subi r24, 0xFF ; 255 e36: 8e 83 std Y+6, r24 ; 0x06 e38: e3 cf rjmp .-58 ; 0xe00 <__vector_1+0x2b2> e3a: 80 91 38 00 lds r24, 0x0038 e3e: 81 60 ori r24, 0x01 ; 1 e40: 80 93 38 00 sts 0x0038, r24 return; e44: e7 c0 rjmp .+462 ; 0x1014 <__vector_1+0x4c6> // Receive the rest of the packet } else { // Skip the destination PAN and address (that's taken care of by harware address recognition!) FASTSPI_READ_FIFO_GARBAGE(4); e46: 80 91 38 00 lds r24, 0x0038 e4a: 8e 7f andi r24, 0xFE ; 254 e4c: 80 93 38 00 sts 0x0038, r24 e50: 8f e7 ldi r24, 0x7F ; 127 e52: 80 93 2f 00 sts 0x002F, r24 e56: 80 91 2e 00 lds r24, 0x002E e5a: 88 23 and r24, r24 e5c: 0c f0 brlt .+2 ; 0xe60 <__vector_1+0x312> e5e: fb cf rjmp .-10 ; 0xe56 <__vector_1+0x308> e60: 1e 82 std Y+6, r1 ; 0x06 e62: 8e 81 ldd r24, Y+6 ; 0x06 e64: 84 30 cpi r24, 0x04 ; 4 e66: 90 f4 brcc .+36 ; 0xe8c <__vector_1+0x33e> e68: 80 91 30 00 lds r24, 0x0030 e6c: 99 27 eor r25, r25 e6e: 82 70 andi r24, 0x02 ; 2 e70: 90 70 andi r25, 0x00 ; 0 e72: 00 97 sbiw r24, 0x00 ; 0 e74: 59 f0 breq .+22 ; 0xe8c <__vector_1+0x33e> e76: 10 92 2f 00 sts 0x002F, r1 e7a: 80 91 2e 00 lds r24, 0x002E e7e: 88 23 and r24, r24 e80: 0c f0 brlt .+2 ; 0xe84 <__vector_1+0x336> e82: fb cf rjmp .-10 ; 0xe7a <__vector_1+0x32c> e84: 8e 81 ldd r24, Y+6 ; 0x06 e86: 8f 5f subi r24, 0xFF ; 255 e88: 8e 83 std Y+6, r24 ; 0x06 e8a: eb cf rjmp .-42 ; 0xe62 <__vector_1+0x314> e8c: 80 91 38 00 lds r24, 0x0038 e90: 81 60 ori r24, 0x01 ; 1 e92: 80 93 38 00 sts 0x0038, r24 //FASTSPI_READ_FIFO_NO_WAIT((BYTE*) &rfSettings.panId, 2); //FASTSPI_READ_FIFO_NO_WAIT((BYTE*) &rfSettings.myAddr, 2); //FASTSPI_READ_FIFO_NO_WAIT((BYTE*) &destaddr, 2); // Read the source address FASTSPI_READ_FIFO_NO_WAIT((BYTE*) &rfSettings.pRxInfo->srcAddr, 2); e96: 80 91 38 00 lds r24, 0x0038 e9a: 8e 7f andi r24, 0xFE ; 254 e9c: 80 93 38 00 sts 0x0038, r24 ea0: 8f e7 ldi r24, 0x7F ; 127 ea2: 80 93 2f 00 sts 0x002F, r24 ea6: 80 91 2e 00 lds r24, 0x002E eaa: 88 23 and r24, r24 eac: 0c f0 brlt .+2 ; 0xeb0 <__vector_1+0x362> eae: fb cf rjmp .-10 ; 0xea6 <__vector_1+0x358> eb0: 1e 82 std Y+6, r1 ; 0x06 eb2: 8e 81 ldd r24, Y+6 ; 0x06 eb4: 82 30 cpi r24, 0x02 ; 2 eb6: c8 f4 brcc .+50 ; 0xeea <__vector_1+0x39c> eb8: 10 92 2f 00 sts 0x002F, r1 ebc: 80 91 2e 00 lds r24, 0x002E ec0: 88 23 and r24, r24 ec2: 0c f0 brlt .+2 ; 0xec6 <__vector_1+0x378> ec4: fb cf rjmp .-10 ; 0xebc <__vector_1+0x36e> ec6: 8e 81 ldd r24, Y+6 ; 0x06 ec8: 28 2f mov r18, r24 eca: 33 27 eor r19, r19 ecc: 80 91 fa 01 lds r24, 0x01FA ed0: 90 91 fb 01 lds r25, 0x01FB ed4: 82 0f add r24, r18 ed6: 93 1f adc r25, r19 ed8: fc 01 movw r30, r24 eda: 31 96 adiw r30, 0x01 ; 1 edc: 80 91 2f 00 lds r24, 0x002F ee0: 80 83 st Z, r24 ee2: 8e 81 ldd r24, Y+6 ; 0x06 ee4: 8f 5f subi r24, 0xFF ; 255 ee6: 8e 83 std Y+6, r24 ; 0x06 ee8: e4 cf rjmp .-56 ; 0xeb2 <__vector_1+0x364> eea: 80 91 38 00 lds r24, 0x0038 eee: 81 60 ori r24, 0x01 ; 1 ef0: 80 93 38 00 sts 0x0038, r24 // Read the packet payload FASTSPI_READ_FIFO_NO_WAIT(rfSettings.pRxInfo->pPayload, rfSettings.pRxInfo->length); ef4: 80 91 38 00 lds r24, 0x0038 ef8: 8e 7f andi r24, 0xFE ; 254 efa: 80 93 38 00 sts 0x0038, r24 efe: 8f e7 ldi r24, 0x7F ; 127 f00: 80 93 2f 00 sts 0x002F, r24 f04: 80 91 2e 00 lds r24, 0x002E f08: 88 23 and r24, r24 f0a: 0c f0 brlt .+2 ; 0xf0e <__vector_1+0x3c0> f0c: fb cf rjmp .-10 ; 0xf04 <__vector_1+0x3b6> f0e: 1e 82 std Y+6, r1 ; 0x06 f10: 8e 81 ldd r24, Y+6 ; 0x06 f12: 28 2f mov r18, r24 f14: 33 27 eor r19, r19 f16: e0 91 fa 01 lds r30, 0x01FA f1a: f0 91 fb 01 lds r31, 0x01FB f1e: 85 81 ldd r24, Z+5 ; 0x05 f20: 99 27 eor r25, r25 f22: 87 fd sbrc r24, 7 f24: 90 95 com r25 f26: 28 17 cp r18, r24 f28: 39 07 cpc r19, r25 f2a: d4 f4 brge .+52 ; 0xf60 <__vector_1+0x412> f2c: 10 92 2f 00 sts 0x002F, r1 f30: 80 91 2e 00 lds r24, 0x002E f34: 88 23 and r24, r24 f36: 0c f0 brlt .+2 ; 0xf3a <__vector_1+0x3ec> f38: fb cf rjmp .-10 ; 0xf30 <__vector_1+0x3e2> f3a: e0 91 fa 01 lds r30, 0x01FA f3e: f0 91 fb 01 lds r31, 0x01FB f42: 8e 81 ldd r24, Y+6 ; 0x06 f44: 28 2f mov r18, r24 f46: 33 27 eor r19, r19 f48: 86 81 ldd r24, Z+6 ; 0x06 f4a: 97 81 ldd r25, Z+7 ; 0x07 f4c: f9 01 movw r30, r18 f4e: e8 0f add r30, r24 f50: f9 1f adc r31, r25 f52: 80 91 2f 00 lds r24, 0x002F f56: 80 83 st Z, r24 f58: 8e 81 ldd r24, Y+6 ; 0x06 f5a: 8f 5f subi r24, 0xFF ; 255 f5c: 8e 83 std Y+6, r24 ; 0x06 f5e: d8 cf rjmp .-80 ; 0xf10 <__vector_1+0x3c2> f60: 80 91 38 00 lds r24, 0x0038 f64: 81 60 ori r24, 0x01 ; 1 f66: 80 93 38 00 sts 0x0038, r24 // Read the footer to get the RSSI value FASTSPI_READ_FIFO_NO_WAIT((BYTE*) pFooter, 2); f6a: 80 91 38 00 lds r24, 0x0038 f6e: 8e 7f andi r24, 0xFE ; 254 f70: 80 93 38 00 sts 0x0038, r24 f74: 8f e7 ldi r24, 0x7F ; 127 f76: 80 93 2f 00 sts 0x002F, r24 f7a: 80 91 2e 00 lds r24, 0x002E f7e: 88 23 and r24, r24 f80: 0c f0 brlt .+2 ; 0xf84 <__vector_1+0x436> f82: fb cf rjmp .-10 ; 0xf7a <__vector_1+0x42c> f84: 1e 82 std Y+6, r1 ; 0x06 f86: 8e 81 ldd r24, Y+6 ; 0x06 f88: 82 30 cpi r24, 0x02 ; 2 f8a: b8 f4 brcc .+46 ; 0xfba <__vector_1+0x46c> f8c: 10 92 2f 00 sts 0x002F, r1 f90: 80 91 2e 00 lds r24, 0x002E f94: 88 23 and r24, r24 f96: 0c f0 brlt .+2 ; 0xf9a <__vector_1+0x44c> f98: fb cf rjmp .-10 ; 0xf90 <__vector_1+0x442> f9a: 8e 81 ldd r24, Y+6 ; 0x06 f9c: 28 2f mov r18, r24 f9e: 33 27 eor r19, r19 fa0: ce 01 movw r24, r28 fa2: 01 96 adiw r24, 0x01 ; 1 fa4: 82 0f add r24, r18 fa6: 93 1f adc r25, r19 fa8: fc 01 movw r30, r24 faa: 33 96 adiw r30, 0x03 ; 3 fac: 80 91 2f 00 lds r24, 0x002F fb0: 80 83 st Z, r24 fb2: 8e 81 ldd r24, Y+6 ; 0x06 fb4: 8f 5f subi r24, 0xFF ; 255 fb6: 8e 83 std Y+6, r24 ; 0x06 fb8: e6 cf rjmp .-52 ; 0xf86 <__vector_1+0x438> fba: 80 91 38 00 lds r24, 0x0038 fbe: 81 60 ori r24, 0x01 ; 1 fc0: 80 93 38 00 sts 0x0038, r24 rfSettings.pRxInfo->rssi = pFooter[0]; fc4: e0 91 fa 01 lds r30, 0x01FA fc8: f0 91 fb 01 lds r31, 0x01FB fcc: 8c 81 ldd r24, Y+4 ; 0x04 fce: 81 87 std Z+9, r24 ; 0x09 SET_GLED(); fd0: 80 91 23 00 lds r24, 0x0023 fd4: 84 60 ori r24, 0x04 ; 4 fd6: 80 93 23 00 sts 0x0023, r24 halWait(50000); fda: 80 e5 ldi r24, 0x50 ; 80 fdc: 93 ec ldi r25, 0xC3 ; 195 fde: 0e 94 3a 01 call 0x274 CLR_GLED(); fe2: 80 91 23 00 lds r24, 0x0023 fe6: 8b 7f andi r24, 0xFB ; 251 fe8: 80 93 23 00 sts 0x0023, r24 // halWait(50000); // Notify the application about the received _data_ packet if the CRC is OK if (((frameControlField & (BASIC_RF_FCF_BM)) == BASIC_RF_FCF_ACK) && (pFooter[1] & BASIC_RF_CRC_OK_BM)) fec: 89 81 ldd r24, Y+1 ; 0x01 fee: 9a 81 ldd r25, Y+2 ; 0x02 ff0: 8f 7d andi r24, 0xDF ; 223 ff2: 28 e8 ldi r18, 0x88 ; 136 ff4: 81 36 cpi r24, 0x61 ; 97 ff6: 92 07 cpc r25, r18 ff8: 69 f4 brne .+26 ; 0x1014 <__vector_1+0x4c6> ffa: 8d 81 ldd r24, Y+5 ; 0x05 ffc: 88 23 and r24, r24 ffe: 54 f4 brge .+20 ; 0x1014 <__vector_1+0x4c6> { rfSettings.pRxInfo = basicRfReceivePacket(rfSettings.pRxInfo); 1000: 80 91 fa 01 lds r24, 0x01FA 1004: 90 91 fb 01 lds r25, 0x01FB 1008: 0e 94 65 00 call 0xca 100c: 90 93 fb 01 sts 0x01FB, r25 1010: 80 93 fa 01 sts 0x01FA, r24 1014: 26 96 adiw r28, 0x06 ; 6 1016: f8 94 cli 1018: de bf out 0x3e, r29 ; 62 101a: cd bf out 0x3d, r28 ; 61 101c: df 91 pop r29 101e: cf 91 pop r28 1020: ff 91 pop r31 1022: ef 91 pop r30 1024: bf 91 pop r27 1026: af 91 pop r26 1028: 9f 91 pop r25 102a: 8f 91 pop r24 102c: 7f 91 pop r23 102e: 6f 91 pop r22 1030: 5f 91 pop r21 1032: 4f 91 pop r20 1034: 3f 91 pop r19 1036: 2f 91 pop r18 1038: 0f 90 pop r0 103a: 0f be out 0x3f, r0 ; 63 103c: 0f 90 pop r0 103e: 1f 90 pop r1 1040: 18 95 reti