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/*
 * vivi/arch/sa1100/arch.c: ÇÁ·Î¼¼¼­ÇÏ°í °ü·ÃµÈ ³ðµé
 *
 * Copyright (C) 2002 MIZI Research, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 * 
 * Author: Janghoon Lyu 
 * Date  : $Date: 2002/10/11 01:31:35 $
 *
 * $Revision: 1.5 $
 * $Id: proc.c,v 1.5 2002/10/11 01:31:35 nandy Exp $
 *
 *
 * History
 *
 * 2002-07-12: Janghoon Lyu 
 *    - Initial code
 *
 */

#include "config.h"
#include "machine.h"
#include "mmu.h"
#include "command.h"
#include 

#define CLOCK_TICK_RATE		3686400
/*
 * time_wait(): wait macthing OS timer
 *
 * sec: is time value. valid range is 0 to 500
 * unit: if value is 0, unit is u-sec. if value is 1, unit is m-sec.
 */
static void time_wait(unsigned int sec, int unit)
{
	unsigned int ticks;

	OSMR0 = 0;
	OSCR = 0;
	OSSR = OSSR_M0;		/* clear match status channel 0 */

	if (unit == 0) {
		ticks = (CLOCK_TICK_RATE * (sec)) / (1000 * 1000);
	} else {
		ticks = (CLOCK_TICK_RATE * (sec)) / (1000);
	}

	OSMR0 = (OSCR + ticks);
	while (!(OSSR & OSSR_M0)) ;
}

static void time_delay(unsigned int sec, int unit)
{
	unsigned int remain = sec;

	while (remain > 0) {
		if (remain > 500) {
			sec = 500;
		} else {
			sec = remain;
		}
		time_wait(sec, unit);
		remain -= sec;
	}
}

void arch_udelay(unsigned int usec)
{
	time_delay(usec, 0);
}

void arch_mdelay(unsigned int msec)
{
	time_delay(msec, 1);
}

void init_time(void)
{
	OIER = 0x0;		/* disable all interrupts */
	OWER = 0x0;	
	OSSR = 0x0;		/* clear all status bits */

	OIER |= OIER_E0;	/* enable a interrupt of channel 0 */
}

/*
 * Perform a soft reset of the system.  Put the CPU into the
 * same state as it would be if it had been reset, and branch
 * to what would be the reset vector.
 *
 * loc: location to jump to for soft reset
 */
void processor_reset(unsigned long loc)
{
	cache_clean_invalidate();
	tlb_invalidate();

__asm__(
	"mov	ip, #0\n"
	"mcr	p15, 0, ip, c7, c7, 0\n"	/* invalidate I,D caches */
	"mcr	p15, 0, ip, c7, c10, 4\n"	/* drain WB */
	"mcr	p15, 0, ip, c8, c7, 0\n"	/* invalidate I & D TLBs */
	"mrc	p15, 0, ip, c1, c0, 0\n"	/* ctrl register */
	"bic	ip, ip, #0x000f\n"		/* ............wcam */
	"bic	ip, ip, #0x1100\n"		/* ...i...s........ */
	"mcr	p15, 0, ip, c1, c0, 0\n"	/* ctrl register */
	"mov	pc, %0\n"
	: : "r" (loc) );

}

void command_reset(int argc, const char **argv)
{
	char mode;
	if (argc == 2) {
		mode = *argv[1];	
	} else {
		mode = 'h';
	}

	if (mode == 's') {
		/* Jump into ROM at address 0 */
		processor_reset(0);
	} else {
		/* Use on-chip reset capability */
		RSRR = RSRR_SWR;
	}
}

user_command_t reset_cmd = {
	"reset",
	command_reset,
	NULL,
	"reset \t\t\t\t-- Reset the system"
};