www.pudn.com > mizi_vivi.rar > exilien102.c

/*
 * vivi/arch/sa1100/exilien102.c: specific EXILIEN102
 *
 * This code is GPL
 *
 * Author: Janghoon Lyu 
 * Date  : $Date: 2002/08/21 06:39:00 $
 *
 * $Revision: 1.2 $
 * 
 */

#include "config.h"
#include "machine.h"
#include "hardware.h"
#include "priv_data.h"
#include "command.h"
#include "boot_kernel.h"
#include "mtd/map.h"
#include "vivi.h"

mtd_partition_t default_mtd_partitions[] = {
	{
		name:		"vivi",
		offset:		0,
		size:		0x00040000,
		flag:		0
	}, {
		name:		"param",
		offset:		0x00040000,
		size:		0x00040000,
		flag:		0
	}, {
		name:		"kernel",
		offset:		0x00080000,
		size:		0x000C0000,
		flag:		0
	} 
};
int default_nb_part = ARRAY_SIZE(default_mtd_partitions);

vivi_parameter_t default_vivi_parameters[] = {
        { "mach_type",                  MACH_TYPE,      NULL }, 
        { "media_type",                 MT_NOR_FLASH,   NULL }, 
        { "boot_mem_base",              0xC0000000,     NULL }, 
        { "baudrate",                   UART_BAUD_RATE, NULL }, 
        { "xmodem",                     1,              NULL },
        { "xmodem_one_nak",             0,              NULL },
        { "xmodem_initial_timeout",     300000,         NULL },
        { "xmodem_timeout",             10000000,       NULL },
        { "boot_delay",                 0x1000000,      NULL }, 
        { NULL,                         0,              NULL }
};
int default_nb_params = ARRAY_SIZE(default_vivi_parameters);


char linux_cmd[] = "noinitrd root=/dev/mtdblock3 init=/linuxrc console=ttySA0";

void set_vpp(struct map_info *map, int vpp)
{
	if (vpp == 1) {	/* ENABLE VPP */
		*(volatile int *)(MING_EGPIO0) |= EGPIO_MING_FLASH_WR_EN;
	} else if (vpp == 0) {	/* DISABLE VPP */
		*(volatile int *)(MING_EGPIO0) &= ~EGPIO_MING_FLASH_WR_EN;
	} else {
		printk("set_vpp(): Invalid argument\n");
	}
	return;
}

void set_gpios(void)
{
	unsigned long temp;

	/* set gpios */
	CTL_REG_WRITE(SA1100_GPIO_BASE+SA1100_GPIO_GPDR_OFF, 0x00000000);
	CTL_REG_WRITE(SA1100_GPIO_BASE+SA1100_GPIO_GRER_OFF, 0x00000000);
	CTL_REG_WRITE(SA1100_GPIO_BASE+SA1100_GPIO_GFER_OFF, 0x00000000);
	CTL_REG_WRITE(SA1100_GPIO_BASE+SA1100_GPIO_GEDR_OFF, 0x00000000);
	CTL_REG_WRITE(SA1100_GPIO_BASE+SA1100_GPIO_GAFR_OFF, 0x00000000);

	temp = (CPU_IRQ | nMICOM_RESET);
	CTL_REG_WRITE(SA1100_GPIO_BASE+SA1100_GPIO_GPDR_OFF, temp);
	udelay(10);
	CTL_REG_WRITE(SA1100_GPIO_BASE+SA1100_GPIO_GPSR_OFF, CPU_IRQ);
	CTL_REG_WRITE(SA1100_GPIO_BASE+SA1100_GPIO_GPCR_OFF, nMICOM_RESET);
	udelay(1);
	CTL_REG_WRITE(SA1100_GPIO_BASE+SA1100_GPIO_GPSR_OFF, nMICOM_RESET);
	udelay(1);

	/* set extended gpios */
	*(volatile long *)(MING_EGPIO0) = 0x00000000;
	*(volatile int *)(MING_EGPIO1) = 0x00;
}

int misc(void)
{
	return 0;
}