www.pudn.com > at91rm9200bsp.rar > dbginit.h

 
#define CPU_920T 
#define	ARM920T_SSRAM_SIZE 0x4000 
#define ARM920T_ROMINIT_C_STACK_TOP 0x3000 
#define	ARM920T_INT_ROM_BASE 0x100000 
#define	ART920T_INT_ROM_SIZE 0x020000	 
	 
#define	AT91RM9200_DELAY_VALUE 20 
 
#define MMUCR_M_ENABLE	 (1<<0)  /* MMU enable */ 
#define MMUCR_A_ENABLE	 (1<<1)  /* Address alignment fault enable */ 
#define MMUCR_C_ENABLE	 (1<<2)  /* (data) cache enable */ 
#define MMUCR_W_ENABLE	 (1<<3)  /* write buffer enable */ 
#define MMUCR_PROG32	 (1<<4)  /* PROG32 */ 
#define MMUCR_DATA32	 (1<<5)  /* DATA32 */ 
#define MMUCR_L_ENABLE	 (1<<6)  /* Late abort on earlier CPUs */ 
#define MMUCR_BIGEND	 (1<<7)  /* Big-endian (=1), little-endian (=0) */ 
#define MMUCR_SYSTEM	 (1<<8)  /* System bit, modifies MMU protections */ 
#define MMUCR_ROM	 (1<<9)  /* ROM bit, modifies MMU protections */ 
#define MMUCR_F		 (1<<10) /* Should Be Zero */ 
#define MMUCR_Z_ENABLE	 (1<<11) /* Branch prediction enable on 810 */ 
#define MMUCR_I_ENABLE	 (1<<12) /* Instruction cache enable */ 
#define MMUCR_FB_DISABLE (1<<30) /* nFastBus bit */ 
#define MMUCR_ASYNC_BIT	 (1<<31) /* Async bit*/ 
#define MMUCR_SYNC	 (1<<30) /* Synchronous mode */ 
#define	MMUCR_ASYNC	 (3<<30) /* Asynchronous mode */ 
 
#define MMU_INIT_VALUE (MMUCR_PROG32 | MMUCR_DATA32 | MMUCR_L_ENABLE | \ 
			MMUCR_ROM | MMUCR_W_ENABLE)