www.pudn.com > MPC8241BSP.rar > sysALib.s
/* sysALib.s - Motorola PRPMC600 system-dependent assembly routines */
/* Copyright 1984-2000 Wind River Systems, Inc. */
/* Copyright 1996-2000 Motorola, Inc. All Rights Reserved */
.data
.globl copyright_wind_river
.long copyright_wind_river
/*
modification history
--------------------
01a,28feb00,rhk created (from version 01g, MV2100 BSP).
*/
/*
DESCRIPTION
This module contains system-dependent routines written in assembly
language.
This module must be the first specified in the \f3ld\f1 command used to
build the system. The sysInit() routine is the system start-up code.
*/
#define _ASMLANGUAGE
#include "vxWorks.h"
#include "sysLib.h"
#include "config.h"
#include "regs.h"
#include "asm.h"
/* globals */
.globl _sysInit /* start of system code */
.globl sysInByte
.globl sysOutByte
.globl sysPciInByte
.globl sysPciOutByte
.globl sysPciConfigInByte
.globl sysPciConfigOutByte
.globl sysInWord
.globl sysInWordRev
.globl sysOutWord
.globl sysOutWordRev
.globl sysInLong
.globl sysOutLong
.globl sysInLongRev
.globl sysOutLongRev
.globl sysPciInWord
.globl sysPciOutWord
.globl sysPciConfigInWord
.globl sysPciConfigOutWord
.globl sysPciInLong
.globl sysPciOutLong
.globl sysPciConfigInLong
.globl sysPciConfigOutLong
.globl sysMemProbeSup
.globl sysProbeExc
.globl store_runtime_reg
.globl load_runtime_reg
.globl get_eumbbar
.globl get_kahlua_pcsrbar
.globl sysTimeBaseLGet
.globl sysHid0Get
.globl sysHid1Get
.globl sysHid2Set
.globl sysHid2Get
.globl sysMpc8240GetDec
.globl i2cPciInLong
.globl i2cPciInByte
.globl sysLongLongMove
.globl sysFpSet
.globl sysSioRead
.globl sysSioWrite
.globl runled
/* externals */
.extern usrInit
.text
/*******************************************************************************
*
* sysInit - start after boot
*
* This is the system start-up entry point for VxWorks in RAM, the
* first code executed after booting. It disables interrupts, sets up
* the stack, and jumps to the C routine usrInit() in usrConfig.c.
*
* The initial stack is set to grow down from the address of sysInit(). This
* stack is used only by usrInit() and is never used again. Memory for the
* stack must be accounted for when determining the system load address.
*
* NOTE: This routine should not be called by the user.
*
* RETURNS: N/A
* sysInit (void) /@ THIS IS NOT A CALLABLE ROUTINE @/
*/
_sysInit:
/* disable external interrupts */
xor p0, p0, p0
mtmsr p0 /* clear the MSR register */
/* return from decrementer exceptions */
addis p1, r0, 0x4c00
addi p1, p1, 0x0064 /* load rfi (0x4c000064) to p1 */
stw p1, 0x900(r0) /* store rfi at 0x00000900 */
/* initialize the stack pointer */
lis sp, HIADJ(RAM_LOW_ADRS)
addi sp, sp, LO(RAM_LOW_ADRS)
/* invalidate the MPU's data/instruction caches */
lis r3, 0x0
ori r3, r3, 0xC000 /* r3 has enable and bits set */
or r4, r4, r3 /* set bits */
sync
isync
mtspr HID0, r4 /* HID0 = r4 */
andc r4, r4, r3 /* clear bits */
isync
mtspr HID0, r4
isync
/* disable instruction and data translations in the MMU */
sync
mfmsr r3 /* get the value in msr *
/* clear bits IR and DR */
rlwinm r4, r3, 0, _PPC_MSR_BIT_DR+1, _PPC_MSR_BIT_IR - 1
mtmsr r4 /* set the msr */
sync /* SYNC */
/* initialize the BAT register */
li p3,0 /* clear p0 */
isync
mtspr IBAT0U,p3 /* SPR 528 (IBAT0U) */
isync
mtspr IBAT0L,p3 /* SPR 529 (IBAT0L) */
isync
mtspr IBAT1U,p3 /* SPR 530 (IBAT1U) */
isync
mtspr IBAT1L,p3 /* SPR 531 (IBAT1L) */
isync
mtspr IBAT2U,p3 /* SPR 532 (IBAT2U) */
isync
mtspr IBAT2L,p3 /* SPR 533 (IBAT2L) */
isync
mtspr IBAT3U,p3 /* SPR 534 (IBAT3U) */
isync
mtspr IBAT3L,p3 /* SPR 535 (IBAT3L) */
isync
mtspr DBAT0U,p3 /* SPR 536 (DBAT0U) */
isync
mtspr DBAT0L,p3 /* SPR 537 (DBAT0L) */
isync
mtspr DBAT1U,p3 /* SPR 538 (DBAT1U) */
isync
mtspr DBAT1L,p3 /* SPR 539 (DBAT1L) */
isync
mtspr DBAT2U,p3 /* SPR 540 (DBAT2U) */
isync
mtspr DBAT2L,p3 /* SPR 541 (DBAT2L) */
isync
mtspr DBAT3U,p3 /* SPR 542 (DBAT3U) */
isync
mtspr DBAT3L,p3 /* SPR 543 (DBAT3L) */
isync
/* invalidate entries within both TLBs */
li p1,128
xor p0,p0,p0 /* p0 = 0 */
mtctr p1 /* CTR = 32 */
isync /* context sync req'd before tlbie */
sysALoop:
tlbie p0
addi p0,p0,0x1000 /* increment bits 15-19 */
bdnz sysALoop /* decrement CTR, branch if CTR != 0 */
sync /* sync instr req'd after tlbie */
/* initialize Small Data Area (SDA) start address */
#if FALSE /* XXX TPR NO SDA for now */
lis r2, HIADJ(_SDA2_BASE_)
addi r2, r2, LO(_SDA2_BASE_)
lis r13, HIADJ(_SDA_BASE_)
addi r13, r13, LO(_SDA_BASE_)
#endif
addi sp, sp, -FRAMEBASESZ /* get frame stack */
li r3, BOOT_WARM_AUTOBOOT
/* bl runled*/
b usrInit /* never returns - starts up kernel */
/*****************************************************************************
*
* sysInByte - reads a byte from an io address.
*
* This function reads a byte from a specified io address or from local memory.
* It operates in big-endian mode and does not perform any translation
* operations on either the supplied address or the retrieved data.
*
* RETURNS: byte from address.
*
* UINT8 sysInByte (UINT8 * dataPtr)
*/
sysInByte:
/* Read byte from address */
lbzx r3,r0,r3
/* Return to caller */
bclr 20,0
/******************************************************************************
*
* sysOutByte - writes a byte to an io address.
*
* This function writes a byte to a specified io address or to local memory.
* It operates in big-endian mode and does not perform any translation
* operations on either the supplied address or data.
*
* RETURNS: N/A
*
* void sysOutByte (UINT8 * dataPtr, UINT8 data)
*/
sysOutByte:
/* Write a byte to address */
stbx r4,r0,r3
/* Sync I/O operation */
sync
/* Return to caller */
bclr 20,0
/*****************************************************************************
*
* sysPciInByte - reads a byte from PCI I/O or Memory space
*
* This function reads a byte from a specified PCI I/O or Memory address
* via the PCI bridge chip. This function should be used for access
* to the I/O or Memory mapped registers of a PCI device. Since this routine
* accesses only a single byte of data no address or data manipulation is
* required.
*
* RETURNS: byte from address.
*
* UINT8 sysPciInByte (UINT8 * dataPtr)
*/
sysPciInByte:
/* Read byte from address */
lbzx r3,r0,r3
/* Return to caller */
bclr 20,0
/*****************************************************************************
*
* sysPciOutByte - writes a byte to PCI I/O or Memory space
*
* This function writes a byte to a specified PCI I/O or Memory address
* via the QSPAN bridge chip. This function should be used for writing
* to the I/O or Memory mapped registers of a PCI device. Since this routine
* writes only a single byte of data no address or data manipulation is
* required.
*
* RETURNS: N/A
*
* void sysPciOutByte (UINT8 * dataPtr, UINT8 data)
*/
sysPciOutByte:
/* Write a byte to address */
stbx r4,r0,r3
/* Sync I/O operation */
sync
/* Return to caller */
bclr 20,0
/*****************************************************************************
*
* sysPciConfigInByte - reads a byte from a PCI configuration space address.
*
* This function reads a byte from a specified PCI configuration space
* address. This function uses the indirect PCI configuration space access
* method. It writes the input configuration space address to the CAR and
* then reads the data from the CDR. All reads/writes larger than 8 bits
* use byte swapping.
*
* Register Usage
* r3 - Configuration space address to read from / returned data
* r4 - dummy parameter, used for holding the CAR address
* r5 - dummy parameter, used for holding the CDR address
*
* RETURNS: N/A
*
* UINT8 sysPciConfigInByte (UINT8 * dataPtr, UINT dummy1, UINT dummy2)
*/
sysPciConfigInByte:
andi. r4,r3,3 /* save the 2 LSBs of the PCI addr */
addis r5,r0,HIADJ(PCI_MSTR_PRIMARY_CDR)
ori r5,r5,LO(PCI_MSTR_PRIMARY_CDR)
or r5,r5,r4 /* add the LSBs value to the CDR */
andi. r4,r4,0 /* the config. space address must */
ori r4,r4,3 /* be 4-byte aligned */
andc r3,r3,r4 /* mask off the 2 LSBs */
addis r4,r0,HIADJ(PCI_MSTR_PRIMARY_CAR)
ori r4,r4,LO(PCI_MSTR_PRIMARY_CAR)
stwbrx r3,r0,r4 /* write config. space addr. to CAR */
sync /* ensure memory access is complete */
andi. r3,r3,0
lbz r3,r0(r5) /* read data out of the CDR */
bclr 20,0 /* return to caller */
/*****************************************************************************
*
* sysPciConfigOutByte - writes a byte to a PCI configuration space address.
*
* This function writes a byte to a specified PCI configuration space
* address. This function uses the indirect PCI configuration space access
* method. It writes the input configuration space address to the CAR and
* then writes the data to the CDR. All writes larger than 8 bits use byte
* swapping.
*
* Register Usage
* r3 - Configuration space address to write to
* r4 - data to be written
* r5 - dummy parameter, used for holding the CAR address
* r6 - dummy parameter, used for holding the CDR address
*
* RETURNS: N/A
*
* void sysPciConfigOutByte (UINT8 * dataPtr, UINT8 data,
* UINT dummy1, UINT dummy2)
*/
sysPciConfigOutByte:
andi. r5,r3,3 /* save the 2 LSBs of the PCI addr */
addis r6,r0,HIADJ(PCI_MSTR_PRIMARY_CDR)
ori r6,r6,LO(PCI_MSTR_PRIMARY_CDR)
or r6,r6,r5 /* add the LSBs value to the CDR */
andi. r5,r5,0 /* the config. space address must */
ori r5,r5,3 /* be 4-byte aligned */
andc r3,r3,r5 /* mask off the 2 LSBs */
addis r5,r0,HIADJ(PCI_MSTR_PRIMARY_CAR)
ori r5,r5,LO(PCI_MSTR_PRIMARY_CAR)
stwbrx r3,r0,r5 /* write config. space addr. to CAR */
sync /* ensure memory access is complete */
stb r4,r0(r6) /* write data to CDR */
sync
bclr 20,0 /* return to caller */
/*****************************************************************************
*
* sysInWord - reads a word (16-bit big-endian) from an io address.
*
* This function reads a word from a specified io address or local memory.
* It operates in big-endian mode and does not perform any translation
* operations on either the supplied address or the retrieved data.
*
* RETURNS: 16-bit word from read from address
*
* UINT16 sysInWord (UINT16 * dataPtr)
*/
sysInWord:
/* Read word from address */
lhzx r3,r0,r3
/* Return to caller */
bclr 20,0
/*****************************************************************************
*
* sysInWordRev - reads a word (16-bit byte reversed) from an io address.
*
* This function reads a word from a specified io address, or memory
* and reverses the bytes.
*
* RETURNS: 16 bit word (byte swapped) read from address
*
* UINT16 sysInWordRev (UINT16 * dataPtr)
*/
sysInWordRev:
/* Read word from address */
lhbrx r3,r0,r3
/* Return to caller */
bclr 20,0
/******************************************************************************
*
* sysOutWord - writes a word (16-bit big-endian) to an io address.
*
* This function writes a word to a specified io address or to local memory.
* It operates in big-endian mode and does not perform any translation
* operations on either the supplied address or data.
*
* RETURNS: N/A
*
* void sysOutWord (UINT16 * dataPtr, UINT16 data)
*/
sysOutWord:
/* Write a word to address */
sthx r4,r0,r3
/* Sync I/O operation */
sync
/* Return to caller */
bclr 20,0
/******************************************************************************
*
* sysOutWordRev - writes a word (16-bit little-endian) to an io address.
*
* This function writes a word to a specified io address or to local memory.
* It operates in little-endian mode and swap byte in data.
*
* RETURNS: N/A
*
* void sysOutWord (UINT16 * dataPtr, UINT16 data)
*/
sysOutWordRev:
/* Write a word to address */
sthbrx r4,r0,r3
/* Sync I/O operation */
sync
/* Return to caller */
bclr 20,0
/*****************************************************************************
*
* sysPciInWord - reads a word from PCI I/O or Memory space
*
* This function reads a word from a specified PCI I/O or Memory address
* via the PCI bridge chip. This function should be used for access
* to the I/O or Memory mapped registers of a PCI device. These
* registers are mapped as little-endian, so we byte swap the data in order
* to make the value returned look the same as it would in PCI space.
*
* RETURNS: word from address.
*
* UINT16 sysPciInWord (UINT16 * dataPtr)
*/
sysPciInWord:
/* Read word from address */
lhbrx r3,r0,r3
/* Return to caller */
bclr 20,0
/*****************************************************************************
*
* sysPciOutWord - writes a word to PCI I/O or Memory space
*
* This function writes a word to a specified PCI I/O or Memory address
* via the PCI bridge chip. This function should be used for access
* to the I/O or Memory mapped registers of a PCI device. These
* registers are mapped as little-endian, so we byte swap the data in order
* to make the value written correct for the registers in PCI space.
*
* RETURNS: N/A
*
* void sysPciOutWord (UINT16 * dataPtr, UINT16 data)
*/
sysPciOutWord:
/* Write a word to the address */
sthbrx r4,r0,r3
/* Sync I/O operation */
sync
/* Return to caller */
bclr 20,0
/*****************************************************************************
*
* sysPciConfigInWord - reads a word from a PCI configuration space address.
*
* This function reads a word from a specified PCI configuration space
* address. This function uses the indirect PCI configuration space access
* method. It writes the input configuration space address to the CAR and
* then reads the data from the CDR. All reads/writes larger than 8 bits
* use byte swapping.
*
* Register Usage
* r3 - Configuration space address to read from / returned data
* r4 - dummy parameter, used for holding the CAR address
* r5 - dummy parameter, used for holding the CDR address
*
* RETURNS: N/A
*
* UINT16 sysPciConfigInWord (UINT16 * dataPtr, UINT dummy1, UINT dummy2)
*/
sysPciConfigInWord:
andi. r4,r3,3 /* save the 2 LSBs of the PCI addr */
addis r5,r0,HIADJ(PCI_MSTR_PRIMARY_CDR)
ori r5,r5,LO(PCI_MSTR_PRIMARY_CDR)
or r5,r5,r4 /* add the LSBs value to the CDR */
andi. r4,r4,0 /* the config. space address must */
ori r4,r4,3 /* be 4-byte aligned */
andc r3,r3,r4 /* mask off the 2 LSBs */
addis r4,r0,HIADJ(PCI_MSTR_PRIMARY_CAR)
ori r4,r4,LO(PCI_MSTR_PRIMARY_CAR)
stwbrx r3,r0,r4 /* write config. space addr. to CAR */
sync /* ensure memory access is complete */
andi. r3,r3,0
lhbrx r3,r0,r5 /* read data out of the CDR */
bclr 20,0 /* return to caller */
/*****************************************************************************
*
* sysPciConfigOutWord - writes a word to a PCI configuration space address.
*
* This function writes a word to a specified PCI configuration space
* address. This function uses the indirect PCI configuration space access
* method. It writes the input configuration space address to the CAR and
* then writes the data to the CDR. All writes larger than 8 bits use byte
* swapping.
*
* Register Usage
* r3 - Configuration space address to write to
* r4 - data to be written
* r5 - dummy parameter, used for holding the CAR address
* r6 - dummy parameter, used for holding the CDR address
*
* RETURNS: N/A
*
* void sysPciConfigOutWord (UINT16 * dataPtr, UINT16 data,
* UINT dummy1, UINT dummy2)
*/
sysPciConfigOutWord:
andi. r5,r3,3 /* save the 2 LSBs of the PCI addr */
addis r6,r0,HIADJ(PCI_MSTR_PRIMARY_CDR)
ori r6,r6,LO(PCI_MSTR_PRIMARY_CDR)
or r6,r6,r5 /* add the LSBs value to the CDR */
andi. r5,r5,0 /* the config. space address must */
ori r5,r5,3 /* be 4-byte aligned */
andc r3,r3,r5 /* mask off the 2 LSBs */
addis r5,r0,HIADJ(PCI_MSTR_PRIMARY_CAR)
ori r5,r5,LO(PCI_MSTR_PRIMARY_CAR)
stwbrx r3,r0,r5 /* write config. space addr. to CAR */
sync /* ensure memory access is complete */
sthbrx r4,r0,r6 /* write data to CDR */
sync
bclr 20,0 /* return to caller */
/*****************************************************************************
*
* sysInLong - reads a long (32-bit big-endian) from an io address.
*
* This function reads a long from a specified io address or from local memory.
* It operates in big-endian mode and does not perform any translation
* operations on either the supplied address or the retrieved data.
*
* RETURNS: long (32-bit big-endian) from address
*
* UINT32 sysInLong ( UINT32 * dataPtr)
*/
sysInLong:
/* Read long from address */
lwzx r3,r0,r3
/* Return to caller */
bclr 20,0
/*****************************************************************************
*
* sysInLongRev - reads a long (32-bit little-endian) from an io address.
*
* This function reads a long from a specified io address or from local memory.
* It operates in big-endian mode and swap byte order
*
* RETURNS: long (32-bit little-endian) from address
*
* UINT32 sysInLongRev ( UINT32 * dataPtr)
*/
sysInLongRev:
/* Read long from address */
lwbrx r3,r0,r3
/* Return to caller */
bclr 20,0
/******************************************************************************
*
* sysOutLong - writes a long (32-bit big-endian) to an io address.
*
* This function writes a long to a specified io address or to local memory.
* It operates in big-endian mode and does not perform any translation
* operations on either the supplied address or data.
* This function writes a long to a specified io address.
*
* RETURNS: N/A
*
* void sysOutLong (UINT32 * dataPtr, UINT32 data)
*/
sysOutLong:
/* Write a long to address */
stwx r4,r0,r3
/* Sync I/O operation */
sync
/* Return to caller */
bclr 20,0
/******************************************************************************
*
* sysOutLongRev - writes a long (32-bit little-endian) to an io address.
*
* This function writes a long to a specified io address or to local memory.
* It operates in little-endian mode and swap byte order
* This function writes a long to a specified io address.
*
* RETURNS: N/A
*
* void sysOutLongRev (UINT32 * dataPtr, UINT32 data)
*/
sysOutLongRev:
/* Write a long to address */
stwbrx r4,r0,r3
/* Sync I/O operation */
sync
/* Return to caller */
bclr 20,0
/*****************************************************************************
*
* sysPciInLong - reads a longword from PCI I/O or Memory space
*
* This function reads a longword from a specified PCI I/O or Memory address
* via the PCI bridge chip. This function should be used for access
* to the I/O or Memory mapped registers of a PCI device. These
* registers are mapped as little-endian, so we byte reverse the data in order
* to make the value returned look the same as it would in PCI space.
*
* RETURNS: longword from address.
*
* UINT32 sysPciInLong (UINT32 * dataPtr)
*/
sysPciInLong:
/* Read a longword from the address, and reverse the bytes */
lwbrx r3,r0,r3
/* Return to caller */
bclr 20,0
/*****************************************************************************
*
* sysPciOutLong - writes a longword to PCI I/O or Memory space
*
* This function writes a longword to a specified PCI I/O or Memory address
* via the PCI bridge chip. This function should be used for access
* to the I/O or Memory mapped registers of a PCI device. These
* registers are mapped as little-endian, so we byte reverse the data in order
* to make the value written correct for the registers in PCI space.
*
* RETURNS: N/A
*
* void sysPciOutLong (UINT32 * dataPtr, UINT32 data)
*/
sysPciOutLong:
/* Write a long to the address, reversing the bytes */
stwbrx r4,r0,r3
/* Sync I/O operation */
sync
/* Return to caller */
bclr 20,0
/*****************************************************************************
*
* sysPciConfigInLong - reads a longword from a PCI configuration space address.
*
* This function reads a longword from a specified PCI configuration space
* address. This function uses the indirect PCI configuration space access
* method. It writes the input configuration space address to the CAR and
* then reads the data from the CDR. All reads/writes larger than 8 bits
* use byte swapping.
*
* Register Usage
* r3 - Configuration space address to read from / returned data
* r4 - dummy parameter, used for holding the CAR address
* r5 - dummy parameter, used for holding the CDR address
*
* RETURNS: N/A
*
* UINT32 sysPciConfigInLong (UINT32 * dataPtr, UINT dummy1, UINT dummy2)
*/
sysPciConfigInLong:
addis r4,r0,HIADJ(PCI_MSTR_PRIMARY_CAR)
ori r4,r4,LO(PCI_MSTR_PRIMARY_CAR)
addis r5,r0,HIADJ(PCI_MSTR_PRIMARY_CDR)
ori r5,r5,LO(PCI_MSTR_PRIMARY_CDR)
stwbrx r3,r0,r4 /* write config. space addr. to CAR */
sync /* ensure memory access is complete */
andi. r3,r3,0
lwbrx r3,r0,r5 /* read data out of the CDR */
bclr 20,0 /* return to caller */
/*****************************************************************************
*
* sysPciConfigOutLong - writes a longword to a PCI configuration space address.
*
* This function writes a longword to a specified PCI configuration space
* address. This function uses the indirect PCI configuration space access
* method. It writes the input configuration space address to the CAR and
* then writes the data to the CDR. All writes larger than 8 bits use byte
* swapping.
*
* Register Usage
* r3 - Configuration space address to write to
* r4 - data to be written
* r5 - dummy parameter, used for holding the CAR address
* r6 - dummy parameter, used for holding the CDR address
*
* RETURNS: N/A
*
* void sysPciConfigOutLong (UINT32 * dataPtr, UINT32 data,UINT dummy1,UINT dummy2)
*/
sysPciConfigOutLong:
addis r5,r0,HIADJ(PCI_MSTR_PRIMARY_CAR)
ori r5,r5,LO(PCI_MSTR_PRIMARY_CAR)
addis r6,r0,HIADJ(PCI_MSTR_PRIMARY_CDR)
ori r6,r6,LO(PCI_MSTR_PRIMARY_CDR)
stwbrx r3,r0,r5 /* write config. space addr. to CAR */
sync /* ensure memory access is complete */
stwbrx r4,r0,r6 /* write data to CDR */
sync /* ensure memory access is complete */
bclr 20,0 /* return to caller */
/*******************************************************************************
*
* sysMemProbeSup - sysBusProbe support routine
*
* This routine is called to try to read byte, word, or long, as specified
* by length, from the specified source to the specified destination.
*
* RETURNS: OK if successful probe, else ERROR
STATUS sysMemProbeSup (length, src, dest)
(
int length, // length of cell to test (1, 2, 4, 8, 16) *
char * src, // address to read *
char * dest // address to write *
)
*/
sysMemProbeSup:
addi p7, p0, 0 /* save length to p7 */
xor p0, p0, p0 /* set return status */
cmpwi p7, 1 /* check for byte access */
bne sbpShort /* no, go check for short word access */
lbz p6, 0(p1) /* load byte from source */
stb p6, 0(p2) /* store byte to destination */
sync
isync /* enforce for immediate exception handling */
blr
sbpShort:
cmpwi p7, 2 /* check for short word access */
bne sbpWord /* no, check for word access */
lhz p6, 0(p1) /* load half word from source */
sth p6, 0(p2) /* store half word to destination */
sync
isync /* enforce for immediate exception handling */
blr
sbpWord:
cmpwi p7, 4 /* check for short word access */
bne sysProbeExc /* no, check for double word access */
lwz p6, 0(p1) /* load half word from source */
stw p6, 0(p2) /* store half word to destination */
sync
isync /* enforce for immediate exception handling */
blr
sysProbeExc:
li p0, -1 /* shouldn't ever get here, but... */
blr
/******************************************************************************
*
* sysTimeBaseLGet - Get lower half of Time Base Register
*
* This routine will read the contents the lower half of the Time
* Base Register (TBL - TBR 268).
*
* From a C point of view, the routine is defined as follows:
*
* UINT32 sysTimeBaseLGet(void)
*
* RETURNS: value of TBR 268 (in r3)
*/
sysTimeBaseLGet:
mftb 3
bclr 20,0
/******************************************************************************
*
* sysHid0Get - read from HID0 register SPR1009.
*
* This routine will return the contents of the HID0 (SPR1008)
*
* From a C point of view, the routine is defined as follows:
*
* UINT sysHid0Get()
*
* RETURNS: value of SPR1008 (in r3)
*/
sysHid0Get:
mfspr r3,1008
bclr 20,0
/******************************************************************************
*
* sysHid1Get - read from HID1 register SPR1009.
*
* This routine will return the contents of the HID1 (SPR1009)
*
* From a C point of view, the routine is defined as follows:
*
* UINT sysHid1Get()
*
* RETURNS: value of SPR1009 (in r3)
*/
sysHid1Get:
mfspr r3,1009
bclr 20,0
/******************************************************************************
*
* sysHid2Get - read from HID2 register SPR1011.
*
* This routine will return the contents of the HID2 (SPR1011)
*
* From a C point of view, the routine is defined as follows:
*
* UINT sysHid2Get()
*
* RETURNS: value of SPR1011 (in r3)
*/
sysHid2Get:
mfspr r3,1011
bclr 20,0
/******************************************************************************
*
* sysHid2Set - write data to HID2 register SPR1011.
*
* This routine will store the contents of HID2 (SPR1011) with the data
* supplied in R3.
*
* From a C point of view, the routine is defined as follows:
*
* UINT sysHid2Set(UINT dataValue)
*
* RETURNS: N/A
*/
sysHid2Set:
mtspr 1011,r3
bclr 20,0
/*add for test
UINT32 sysMpc8240GetDec(void)
*/
sysMpc8240GetDec:
mfspr 3,22; /* read the decrementer */
bclr 20,0; /* Here's the actual return */
/*****************************************************************************
*UINT32 i2cPciInLong (UINT32 * dataPtr)
*
* i2cPciInLong - reads a longword from PCI I/O or Memory space
*
* This function reads a longword from a specified PCI I/O or Memory address
* via the PCI bridge chip. This function should be used for access
* to the I/O or Memory mapped registers of a PCI device. These
* registers are mapped as little-endian, so we byte reverse the data in order
* to make the value returned look the same as it would in PCI space.
*
* RETURNS: longword from address.
*
*/
i2cPciInLong:
lwbrx 3,0,3;
bclr 20,0; /* Here's the actual return */
/*****************************************************************************
*UINT8 i2cPciInByte (UINT8 * dataPtr)
*
* i2cPciInByte - reads a byte from PCI I/O or Memory space
*
* This function reads a byte from a specified PCI I/O or Memory address
* via the PCI bridge chip. This function should be used for access
* to the I/O or Memory mapped registers of a PCI device. Since this routine
* accesses only a single byte of data no address or data manipulation is
* required.
*
* RETURNS: byte from address.
*/
i2cPciInByte:
lbzx 3,0,3;
bclr 20,0;
/*************************************************************
* Copy a long long type data from souAddr to destAddr
*
* void sysLongLongMove (UINT32 destAddr, UINT32 souAddr)
*/
sysLongLongMove:
lfd f0, 0(r4)
stfd f0, 0(r3)
sync
/* Return to caller */
bclr 20,0
/********************************************************
* void sysFpSet(ULONG tmp)
*
* Open the FP function.
*/
sysFpSet:
mfmsr r3
ori r3, r3, 0x2000
mtmsr r3
sync
bclr 20,0
/* Add these two function for PC97307, xdg, 11.29 */
/*******************************************************************************
*
* sysSioRead - this function reads a register from the UIO chip
*
* In order to read data from the desired Super IO register, the index register
* must be written to with the offset of the of the register to be read. The
* desired byte of data is then read from the data register.
*
* RETURNS: byte read from data register
*
* From a C point of view, the routine is defined as follows:
UINT8 sysSioRead
(
UINT8 * pSioIndexReg, /@ pointer to SIO index register base addr @/
UINT8 sioRegOffset /@ offset of register to read from @/
)
*/
sysSioRead:
stb r4,0(r3) /* write index register with register offset */
eieio
sync
lbz r3,1(r3) /* retrieve specified reg offset contents */
eieio
sync
bclr 20,0 /* return to caller */
/*******************************************************************************
*
* sysSioWrite - this function writes a register to the UIO chip
*
* In order to write data to the desired Super IO register, the index
* register must be written to with the offset of the of the register to be
* modified. The desired byte of data can then be written via the data
* register.
*
* RETURNS: N/A
*
* From a C point of view, the routine is defined as follows:
void sysSioWrite
(
UINT8 * pSioIndexReg, /@ pointer to SIO index register base addr @/
UINT8 sioRegOffset, /@ offset of register to write to @/
UINT8 data /@ 8-bit data to be written @/
)
*/
sysSioWrite:
stb r4,0(r3) /* write index register with register offset */
eieio
sync
stb r5,1(r3) /* 1st write */
eieio
sync
stb r5,1(r3) /* 2nd write */
eieio
sync
bclr 20,0 /* return to caller */
/**********************************************************
* function: load_runtime_reg
*
* input: r3 - value of eumbbar
* r4 - register offset in embedded utility space
*
* output: r3 - register content
**********************************************************/
load_runtime_reg:
xor r5,r5,r5
or r5,r5,r3 /* save eumbbar */
lwbrx r3,r4,r5
sync
bclr 20, 0
/****************************************************************
* function: store_runtime_reg
*
* input: r3 - value of eumbbar
* r4 - register offset in embedded utility space
* r5 - new value to be stored
*
****************************************************************/
store_runtime_reg:
xor r0,r0,r0
stwbrx r5, r4, r3
sync
bclr 20,0
/**************************************************************************
* get_eumbbar -- return EUMBBAR setting in R3
*/
get_eumbbar:
xor r0,r0,r0
addis r6,r0,HIADJ(CNFG_PCI_HOST_BRDG)
ori r6,r6,LO(CNFG_PCI_HOST_BRDG)
addi r3,r6,MPC8240_CFG_EUMBBAR /* add EUMBBAR offset */
addis r7,r0,HIADJ(PCI_MSTR_PRIMARY_CAR)
ori r7,r7,LO(PCI_MSTR_PRIMARY_CAR)
stwbrx r3,r0,r7 /* write address of EUMBBAR to CAR */
sync
addis r4,r0,HIADJ(PCI_MSTR_PRIMARY_CDR)
ori r4,r4,LO(PCI_MSTR_PRIMARY_CDR)
lwbrx r3,r0,r4 /* read EUMBBAR */
sync /* ensure memory access is complete */
blr
get_kahlua_pcsrbar:
blr
runled:
addis r4,0,0xFF00
/* addis r3,0,0xff00
stw r3,0x0(r4)*/
addis r5,0,0x0000
ori r5,r5,0x0000
alloop1:
addis r3,0,0x0100
stw r3,0x0(r4)
addis r6,0,0x10
mtspr CTR,r6
eieio
sync
write1_loop1:
eieio
bc 16,0,write1_loop1
addis r3,0,0x0300
stw r3,0x0(r4)
addis r6,0,0x10
mtspr CTR,r6
eieio
sync
write_loop1:
eieio
bc 16,0,write_loop1
eieio
sync
addi r5,r5,0x0001
cmpwi r5, 0x3
bne alloop1
blr