www.pudn.com > MPC8241BSP.rar > prpmc600.h
/* prpmc600.h - Motorola PowerPlus board header */
/* Copyright 1984-2000 Wind River Systems, Inc. */
/* Copyright 1996-2000 Motorola, Inc. All Rights Reserved */
/*
modification history
--------------------
01d,21jun00,rhk fixed the constant NUM_SDRAM_BANKS for memory mezz. support.
01c,06jun00,rhk code format changes.
01b,10may00,rhk added Drawbridge support.
01a,25feb00,rhk created. (from ver 01p, mv2100.h)
*/
/*
This file contains I/O addresses and related constants for the
Motorola PrPMC600 PowerPlus board.
*/
#ifndef INCprpmc600h
#define INCprpmc600h
#ifdef __cplusplus
extern "C" {
#endif
#include "mpc8240.h"
/* CPU type */
#define CPU_TYPE ((vxPvrGet() >> 16) & 0xffff)
#define CPU_TYPE_601 0x01 /* PPC 601 CPU */
#define CPU_TYPE_602 0x02 /* PPC 602 CPU */
#define CPU_TYPE_603 0x03 /* PPC 603 CPU */
#define CPU_TYPE_603E 0x06 /* PPC 603e CPU */
#define CPU_TYPE_603EK 0x81 /* PPC 603e-Mpc8240 CPU */
#define CPU_TYPE_603P 0x07 /* PPC 603p CPU */
#define CPU_TYPE_750 0x08 /* PPC 750 CPU */
#define CPU_TYPE_604 0x04 /* PPC 604 CPU */
#define CPU_TYPE_604E 0x09 /* PPC 604e CPU */
#define CPU_TYPE_604R 0x0A /* PPC 604r CPU */
#define CPU_TYPE_8245 0x8081 /* PPC 603e-Mpc8240 CPU */
/* Vital Product Data Support */
#define NUM_SDRAM_BANKS 6 /* max pssible SDRAM banks, mult of 2 */
#define SPD_EEPROM_ADRS0 0xa0 /* i2c address of first SPD EEPROM */
#define VPD_BRD_EEPROM_ADRS 0xa2 /* i2c address of board's SROM */
#define USR_SROM_ADRS 0xa4 /* i2c addr. of user configured SROM */
#define USR_SROM_SIZE 256
#define HOST_BRD_CONFIG 0xa6 /* optional host board configuration */
#define MEM_MEZZ_23 0xaa /* mem. mezzanine SPD banks 2/3 */
#define MEM_MEZZ_45 0xac /* mem. mezzanine SPD banks 4/5 */
#define VPD_BRD_OFFSET 0 /* offset into board's eeprom for
vpd data */
#define EEPROM_TYPE_MPC8240 0
#define I2C_DRV_TYPE EEPROM_TYPE_MPC8240 /* I2C driver type flag */
#define VPD_PKT_LIMIT 25 /* Max number of packets expected */
#define DEFAULT_PCI_CLOCK 33333333
#define DEFAULT_BUS_CLOCK 66700000 /*by wanggeng 20050803*/
/* #define DEFAULT_BUS_CLOCK 100000000 *//* modify by zoutl for 100M */
#define DEFAULT_INTERNAL_CLOCK 250000000
#define DEFAULT_BUS_CLOCK100 100000000
#define DEFAULT_PRODUCT_ID "Unknown"
#define MHZ 1000000
#define NANO2SEC 1000000000 /* num of nanoseconds per second */
#define INCLUDE_PCI /* always include pci */
#define MPC8240_WIN_CNT 5 /* num. CPU - PCI translation windows */
/* Boot Line parameters are stored in the user SROM */
#define NV_RAM_SIZE USR_SROM_SIZE
/* PCI I/O function defines */
#ifndef _ASMLANGUAGE
#ifndef PCI_IN_BYTE
# define PCI_IN_BYTE(x) sysPciInByte (x)
IMPORT UINT8 sysPciInByte (UINT32 address);
#endif
#ifndef PCI_IN_WORD
# define PCI_IN_WORD(x) sysPciInWord (x)
IMPORT UINT16 sysPciInWord (UINT32 address);
#endif
#ifndef PCI_IN_LONG
# define PCI_IN_LONG(x) sysPciInLong (x)
IMPORT UINT32 sysPciInLong (UINT32 address);
#endif
#ifndef PCI_OUT_BYTE
# define PCI_OUT_BYTE(x,y) sysPciOutByte (x,y)
IMPORT void sysPciOutByte (UINT32 address, UINT8 data);
#endif
#ifndef PCI_OUT_WORD
# define PCI_OUT_WORD(x,y) sysPciOutWord (x,y)
IMPORT void sysPciOutWord (UINT32 address, UINT16 data);
#endif
#ifndef PCI_OUT_LONG
# define PCI_OUT_LONG(x,y) sysPciOutLong (x,y)
IMPORT void sysPciOutLong (UINT32 address, UINT32 data);
#endif
#ifndef PCI_INSERT_LONG
# define PCI_INSERT_LONG(a,m,d) sysPciInsertLong((a),(m),(d))
IMPORT void sysPciInsertLong(UINT32 adrs, UINT32 mask, \
UINT32 data);
#endif
#ifndef PCI_INSERT_WORD
# define PCI_INSERT_WORD(a,m,d) sysPciInsertWord((a),(m),(d))
IMPORT void sysPciInsertWord(UINT32 adrs, UINT16 mask, \
UINT16 data);
#endif
#ifndef PCI_INSERT_BYTE
# define PCI_INSERT_BYTE(a,m,d) sysPciInsertByte((a),(m),(d))
IMPORT void sysPciInsertByte(UINT32 adrs, UINT8 mask, \
UINT8 data);
#endif
#endif /* _ASMLANGUAGE */
/* Cache Line Size - 8 32-bit words = 32 bytes */
#define PCI_CLINE_SZ (_CACHE_ALIGN_SIZE/4)
/* Latency Timer value - 255 PCI clocks */
#define PCI_LAT_TIMER 0xff
/* clock rates */
#define SPEED66MHZ 66
#define SPEED83MHZ 83
#define SPEED100MHZ 100
/* memory refresh loop constant */
#define WAIT_REFRESH_COUNT 2083
/* Calculate Memory Bus Rate in Hertz */
#define MEMORY_BUS_SPEED (sysGetBusSpdHertz())
/* System clock (decrementer counter) frequency determination */
#define DEC_CLOCK_FREQ MEMORY_BUS_SPEED
/* CIO clocks and stuff */
#define CIO_RESET_DELAY 5000
#define ZCIO_HZ 2500000 /* 2.5 MHz clock */
#define CIO_INT_VEC 9
#define Z8536_TC ZCIO_HZ
/*
* The PowerPC Decrementer is used as the system clock.
* It is always included in this BSP. The following defines
* are used by the system clock library.
*/
#define SYS_CLK_RATE_MIN 10 /* minimum system clock rate */
#define SYS_CLK_RATE_MAX 5000 /* maximum system clock rate */
/*
* This macro returns the positive difference between two signed ints.
* Useful for determining delta between two successive decrementer reads.
*/
#define DELTA(a,b) ( abs((int)a - (int)b) )
/*
* Auxiliary Clock support is an optional feature that is not supported
* by all BSPs. The following defines are used by the aux clock library.
*/
#define AUX_CLK_RATE_MIN 40 /* min auxiliary clock */
#define AUX_CLK_RATE_MAX 100000 /* max auxiliary clock rate */ /* modify by zoutl 5000->100000 */
/*
* Common I/O synchronizing instructions
*
* Only SYNC is used for the 603e processors. The "eieio" instruction
* is treated as a NOP on the 603e.
*/
#ifndef SYNC
# define SYNC __asm__ volatile ("sync")
#endif /* SYNC */
#ifndef EIEIO_SYNC
# define EIEIO_SYNC __asm__(" isync; sync")
#endif /*EIEIO_SYNC*/
/* Translation macro */
#define TRANSLATE(x,y,z)\
((UINT)(x) - (UINT)(y) + (UINT)(z))
/* BSP configuration error policy */
#define CONTINUE_EXECUTION 0 /* Tolerate VPD/Configuration errors */
#define EXIT_TO_SYSTEM_MONITOR 1 /* Transfer to System Monitor */
#ifdef TOLERATE_CONFIG_ERRORS
# define DEFAULT_BSP_ERROR_BEHAVIOR CONTINUE_EXECUTION
#else
# define DEFAULT_BSP_ERROR_BEHAVIOR EXIT_TO_SYSTEM_MONITOR
#endif
/*
* The following macros define access to PCI and ISA space from the CPU
* and the base addresses of PCI and ISA spaces on the bus (from the CPU
* point of view).
* These macros contain the correct starting addresses and sizes
* for use in the BSP and user programming.
*
*/
#ifdef CHRP_ADRS_MAP
/* Access to PCI ISA I/O space */
# define ISA_MSTR_IO_LOCAL 0xfe000000
# define ISA_MSTR_IO_BUS 0x00000000 /* 0 based addressing */
# define ISA_MSTR_IO_SIZE 0x00010000 /* 64 kbytes max. */
/* Access to PCI I/O space */
# define PCI_MSTR_IO_LOCAL 0xfe800000
# define PCI_MSTR_IO_BUS 0x00800000
# define PCI_MSTR_IO_SIZE 0x00400000 /* 4MB max. */
/* Access to PCI ISA memory space (legacy space) */
# ifdef ISA_MEM_SPACE
# define ISA_MSTR_MEM_LOCAL 0xfd000000
# define ISA_MSTR_MEM_BUS 0x00000000 /* 0 based addressing */
# endif
/* Access to PCI nonprefetchable memory space (including ISA memory space) */
# define PCI_MSTR_MEMIO_LOCAL 0x80000000
# define PCI_MSTR_MEMIO_BUS PCI_MSTR_MEMIO_LOCAL /* 1-1 translation */
/* Access to PCI memory space (prefetchable) */
# define PCI_MSTR_MEM_LOCAL (PCI_MSTR_MEMIO_LOCAL + PCI_MSTR_MEMIO_SIZE)
# define PCI_MSTR_MEM_BUS PCI_MSTR_MEM_LOCAL /* CHRP mode uses */
/* pass through addr */
#else /* PReP map */
/* Access to PCI ISA I/O space */
# define ISA_MSTR_IO_LOCAL 0x80000000
# define ISA_MSTR_IO_BUS 0x00000000 /* 0 based addressing */
# define ISA_MSTR_IO_SIZE 0x00010000 /* 64 kbytes max. */
/* Access to PCI I/O space */
# define PCI_MSTR_IO_LOCAL 0x81000000
# define PCI_MSTR_IO_BUS 0x01000000 /* 0 base + ISA range */
/* Access to PCI ISA memory space (legacy space) */
# ifdef ISA_MEM_SPACE
# define ISA_MSTR_MEM_LOCAL 0xc0000000
# define ISA_MSTR_MEM_BUS 0x00000000 /* 0 based addressing */
# endif
/* Access to PCI nonprefetchable memory space (including ISA memory space) */
# define PCI_MSTR_MEMIO_LOCAL 0xc1000000
# define PCI_MSTR_MEMIO_BUS 0x01000000 /* 0 based addressing */
/* Access to PCI memory space */
# define PCI_MSTR_MEM_LOCAL (PCI_MSTR_MEMIO_LOCAL + PCI_MSTR_MEMIO_SIZE)
# define PCI_MSTR_MEM_BUS (PCI_MSTR_MEMIO_BUS + PCI_MSTR_MEMIO_SIZE)
#endif /* CHRP_ADRS_MAP */
/*
* The following describes the additional address spaces used for
* PCI space configuration on the Mpc8240 processor. The addresses
* for each type of mapping (CHRP or PReP) are fixed and cannot be
* modified.
*/
#ifdef CHRP_ADRS_MAP
/* additional PCI CHRP memory map defines (as seen from the CPU) */
# define PCI_MSTR_PRIMARY_CAR 0xfec00000 /* PCI config address reg */
# define PCI_MSTR_PRIMARY_CAR_SIZE 0x00001000 /* use 4KB page tbl entry */
# define PCI_MSTR_PRIMARY_CDR 0xfee00000 /* PCI config data reg */
# define PCI_MSTR_PRIMARY_CDR_SIZE 0x00001000 /* use 4KB page tbl entry */
# define PCI_MSTR_IACK_BASE_ADRS 0xfef00000 /* PCI interrupt acknowl */
# define PCI_MSTR_IACK_SIZE 0x00001000 /* use 4KB page tbl entry */
# define PCI_MSTR_IACK_WNDW_ADRS PCI_MSTR_IACK_BASE_ADRS
#else /* PReP map */
/* additional PCI PREP memory map defines (as seen from the CPU) */
# define PCI_MSTR_PRIMARY_CAR (ISA_MSTR_IO_LOCAL + 0xcf8) /* PCI CAR */
# define PCI_MSTR_PRIMARY_CDR (ISA_MSTR_IO_LOCAL + 0xcfc) /* PCI CDR */
# define PCI_MSTR_DIRECT_MAP_ADRS (ISA_MSTR_IO_LOCAL + 0x00800000) /* base */
/* of direct PCI config */
/* space access */
# define PCI_MSTR_DIRECT_SIZE 0x00800000 /* 8MB */
# define PCI_MSTR_IACK_BASE_ADRS 0xbffffff0 /* PCI interrupt acknowl */
# define PCI_MSTR_IACK_SIZE 0x00001000 /* use 4KB page tbl entry */
# define PCI_MSTR_IACK_WNDW_ADRS 0xbffff000
# define PCI_CHRP_PRIMARY_CAR 0xfec00000 /* CHRP CAR and CDR adrs */
# define PCI_CHRP_PRIMARY_CDR 0xfee00000 /* for switch to PReP */
#endif /* CHRP_ADRS_MAP */
/*
* setup the Base Address for the Mpc8240 registers, use the 1MB block
* just below the top of PCI Memory space.
*/
#ifdef CHRP_ADRS_MAP
# define MPC8240_REGISTERS_BASE 0xfcf00000/*0xa0000000*/
#else
# define MPC8240_REGISTERS_BASE 0xfef00000
#endif /* CHRP_ADRS_MAP */
#define FLASH_BASE_ADRS 0x70000000/*0xff000000*/
#define FLASH_MEM_SIZE 0x01000000 /*16M bytes*/
/* defines for PCI AUTO_CONFIG */
#define ISA_LEGACY_SIZE 0x00004000
/*
* PCI MASTER MEMORY WINDOW LIMITS for sysBusProbe
*
* These values are strictly defined by the base memory addresses and window
* sizes of the spaces defined above. These values must be correct for the
* sysBusProbe() memory range checks for the PCI bus to work properly.
*/
#define PCI_MSTR_MEM_LO_ADRS PCI_MSTR_MEMIO_LOCAL
#define PCI_MSTR_MEM_HI_ADRS (PCI_MSTR_MEM_LOCAL + PCI_MSTR_MEM_SIZE)
#define PCI_MSTR_IO_LO_ADRS ISA_MSTR_IO_LOCAL
#define PCI_MSTR_IO_HI_ADRS (PCI_MSTR_IO_LOCAL + PCI_MSTR_IO_SIZE)
/*
* Map PCI memory access to local CPU space
*
* PCI_SLV_MEM_LOCAL - Base address of Local CPU space
* PCI_SLV_MEM_BUS - Base address of local memory as seen from PCI Bus
* PCI_SLV_MEM_SIZE - Size of Window for Local space access
*/
/*
* The macro PCI_SLV_MEM_BUS sets the base value for PCI Mem space access of
* local memory. A PCI memory device that puts this address onto the bus will
* access local memory at the address specified by PCI_SLV_MEM_LOCAL
*/
#ifdef CHRP_ADRS_MAP
# define PCI_SLV_MEM_BUS 0x00000000
#else /* PReP map */
# define PCI_SLV_MEM_BUS 0x80000000
#endif /* CHRP_ADRS_MAP */
#define PCI2DRAM_BASE_ADRS PCI_SLV_MEM_BUS /* needed for usrNetwork.c */
/*
* The macro PCI_SLV_MEM_LOCAL is the base at which local memory will appear
* in CPU space.
*/
#define PCI_SLV_MEM_LOCAL LOCAL_MEM_LOCAL_ADRS
/*
* The macro PCI_SLV_MEM_SIZE specify the range of PCI
* memory space as it appears on the PCI bus.
*/
#ifdef CHRP_ADRS_MAP
# define PCI_SLV_MEM_SIZE 0x40000000 /* CHRP max is 1 GB */
#else /* PReP map */
# define PCI_SLV_MEM_SIZE 0x80000000 /* PReP max is 2GB */
#endif /* CHRP_ADRS_MAP */
/* PCI device select definitions */
#define PCI_DEVSEL_PHB 0 /* Mpc8240 PCI host bridge */
#define PCI_DEVSEL_ETHERNET 14 /* DEC21143 Ethernet */
#define PCI_DEVSEL_PCMIPT1S1 16 /* PC-MIP Type 1 Slot 1 (PMC) */
#define PCI_DEVSEL_PCMIPT1S2 17 /* PC-MIP Type 1 Slot 2 */
#define PCI_DEVSEL_PCMIPT2S1 18 /* PC-MIP Type 2 Slot 1 */
#define PCI_DEVSEL_PCMIPT2S2 19 /* PC-MIP Type 2 Slot 2 */
/*
* PCI Config Space device addresses based on their device number
*
* Bit 32 is set to enable CONFIG_DATA accesses to PCI Cycles
*/
#define CNFG_START_SEARCH 0x5800 /* PCI Space starting offset */
#define CNFG_PCI_HOST_BRDG 0x80000000 /* Mpc8240 PCI host bridge */
#define CNFG_IBC_ADRS 0x80005800 /* IBC */
#define CNFG_SCSI_ADRS 0x80006000 /* SCSI */
#define CNFG_LN_ADRS 0x80007000 /* Ethernet Device */
#define CNFG_VGA_ADRS 0x80007800 /* Graphics Device */
#define CNFG_PCMIPT1S1_ADRS 0x80008000 /* PC-MIP Type 1 Slot 1 (PMC) */
#define CNFG_PCMIPT1S2_ADRS 0x80008800 /* PC-MIP Type 1 Slot 2 */
#define CNFG_PCMIPT2S1_ADRS 0x80009000 /* PC-MIP Type 2 Slot 1 */
#define CNFG_PCMIPT2S2_ADRS 0x80009800 /* PC-MIP Type 2 Slot 2 */
/* Special dec21143 configuration device driver area register */
#define PCI_CFG_21143_DA 0x40
/* Number of PCI devices */
#define NUM_PCI_DEVS 4
/* PCI Device/Vendor IDs */
#define PCI_ID_LN_DEC21140 0x00091011 /* Id DEC chip 21140 */
#define PCI_ID_LN_DEC21143 0x00191011 /* Id DEC chip 21143 */
#define PCI_ID_LN_I82559ER 0x12098086 /* Id for I82559ER chip */
#define PCI_ID_LN_I82559 0x12298086 /* Id for Intel 82559 */
#define PCI_ID_SCSI 0x00031000 /* Id for SYM53C825/75 Chips */
#define PCI_ID_SEC_SCSI 0x00011000 /* Id for SYM53C810A Chip */
#define PCI_ID_NCR810 0x00011000 /* Id for SYM53C810A Chip */
#define PCI_ID_NCR860 0x00061000 /* Id for SYM53C860 Chip */
#define PCI_ID_NCR825 0x00031000 /* Id for SYM53C825/75 Chips*/
#define PCI_ID_LN_DEC21040 0x00021011 /* Id DEC chip 21040 */
#define PCI_ID_5434 0x00a81013 /* Id for CL-GD534 chip */
#define PCI_ID_5436 0x00ac1013 /* Id for CL-GD536 chip */
#define PCI_ID_BR_DEC21150 0x00221011 /* Id DEC 21150 PCI bridge */
#define PCI_ID_MPC8240_CFG 0x00031057 /* Id for Mpc8240 config regs */
#define PCI_ID_BR_DEC21554 0x00461011 /* Id DEC 21554 PCI bridge */
#define PCI_ID_UNIVERSE 0x000010e3 /* Id for Universe VME chip */
#define PCI_ID_HAWK 0x48031057 /* Id for HAWK PHB */
#define PCI_ID_IBC 0x05861106 /* Id for VT82586 PBC */
#define PCI_ID_IDE 0x05711106 /* Id for VT82586 IDE */
/* the following one line is add by xdg */
#define PCI_ID_W83C553 0x056510ad /* Id for PCI/ISA bridge in W83C553 */
/* PCI to CPU definitions */
#ifdef LOCAL_MEM_AUTOSIZE
# define DRAM_SIZE ((ULONG)sysPhysMemTop() - LOCAL_MEM_LOCAL_ADRS)
#else
# define DRAM_SIZE (LOCAL_MEM_SIZE - LOCAL_MEM_LOCAL_ADRS)
#endif
/*
* Allocate PCI Memory and I/O Space Offsets for PCI devices
*
* All devices on the primary and secondary busses are allocated 64 kb spaces.
* The PMC Span can control up to four PMCs.
*/
#define SCSI_DEV_SPACE 0x10000
#define LAN_DEV_SPACE 0x20000
#define VGA_DEV_SPACE 0x30000
#define PMC_DEV_SPACE 0x40000
#define LAN2_DEV_SPACE 0x60000
#define SCSI_DEV_SPACE2 0x70000
#define SPAN_IO_DEV_SPACE 0x80000
#define SPAN_IO_DEV_SIZE 0x40000
#define SPAN_MEM_DEV_SPACE 0x02000000
#define SPAN_MEM_DEV_SIZE 0x01000000
#define SPAN_PREF_DEV_SPACE 0x01000000
#define SPAN_PREF_DEV_SIZE 0x01000000
/* PCI view of PCI I/O Space for PCI devices */
#define PCI_IO_SCSI_ADRS (PCI_MSTR_IO_BUS + SCSI_DEV_SPACE) /* 53C825 */
#define PCI_IO_LN_ADRS (PCI_MSTR_IO_BUS + LAN_DEV_SPACE) /* PCnet */
#define PCI_IO_VGA_ADRS (PCI_MSTR_IO_BUS + VGA_DEV_SPACE) /* GD5434 */
#define PCI_IO_PMC_ADRS (PCI_MSTR_IO_BUS + PMC_DEV_SPACE) /* extra */
#define PCI_IO_LN2_ADRS (PCI_MSTR_IO_BUS + LAN2_DEV_SPACE) /* 21040 */
#define PCI_IO_SCSI_ADRS2 (PCI_MSTR_IO_BUS + SCSI_DEV_SPACE2) /* 53C825A*/
/* Allocated base address of HW devices as seen from CPU */
#define SCSI_BASE_ADRS ( PCI_MSTR_IO_LOCAL + SCSI_DEV_SPACE )
#define LAN_BASE_ADRS ( PCI_MSTR_IO_LOCAL + LAN_DEV_SPACE )
#define LAN2_BASE_ADRS ( PCI_MSTR_IO_LOCAL + LAN2_DEV_SPACE )
#define SCSI_BASE_ADRS2 ( PCI_MSTR_IO_LOCAL + SCSI_DEV_SPACE2 )
/*
* System I/O address definitions
*
* The system resources are mapped into the lower 1MB address
* range of FLASH/ROM bank 0 (FFE00000 - FFEFFFFF).
*/
#define PRPMC600_SIO_BASE 0xFFE00000 /* base address of system I/O */
#define PRPMC600_SIO_SIZE 0x00100000 /* base address of system I/O */
#define PRPMC600_SYS_STAT_REG1 (PRPMC600_SIO_BASE+0x00000)
#define PRPMC600_SYS_STAT_REG2 (PRPMC600_SIO_BASE+0x01000)
#define PRPMC600_CONFIG_HDR_REG (PRPMC600_SIO_BASE+0x04000)
#define PRPMC600_COM1_UART (PRPMC600_SIO_BASE+0x10000)
/* Bit masks and bit definitions for system status register #1 */
#define PRPMC600_RESET 0x80 /* hard reset of prpmc600 board */
#define PRPMC600_MONARCH 0x40 /* if set prpmc600 is in slave mode */
#define PRPMC600_ABORT 0x10 /* state of the abort signal */
#define PRPMC600_EEPROM_WP 0x08 /* EEPROM write protect bit */
#define PRPMC600_FLASH_WP 0x04 /* INTEL only, FLASH write protect */
#define PRPMC600_FLASH_BSY 0x02 /* AMD only, FLASH device busy */
#define PRPMC600_REF_CLK 0x01 /* reference clock */
#define PRPMC600_REF_CLK_BIT 0x00 /* reference clock bit position */
/* bit masks for system status register #2 */
#define PRPMC600_BD_FAIL 0x80 /* Board fail indicator */
#define PRPMC600_LED_1 0x40 /* LED 1 bit, for future use */
#define PRPMC600_LED_2 0x20 /* LED 2 bit, for future use */
#define PRPMC600_LED_3 0x10 /* LED 3 bit, for future use */
#define PRPMC600_LED_4 0x08 /* LED 4 bit, for future use */
/* Configuration Header register bit masks */
#define PRPMC600_CFG3 0x10 /* 0 = jumper in header position 7-8 */
#define PRPMC600_CFG2 0x20 /* 0 = jumper in header position 5-6 */
#define PRPMC600_CFG1 0x40 /* 0 = jumper in header position 3-4 */
#define PRPMC600_CFG0 0x80 /* 0 = jumper in header position 1-2 */
#define BUS_SPEED_MASK 0xF8
/* programmable interrupt controller (PIC) */
#define PIC_REG_ADDR_INTERVAL 1 /* address diff of adjacent regs. */
/* programmable interrupt timers */
#define PIT_BASE_ADR SL82565_TMR1_CNT0 /* timeraddrs */
#define PIT_REG_ADDR_INTERVAL 1
#define PIT_CLOCK 1193180
/* PC97307 UART1&2 added by xdg, 00.10.16*/
#define NS_COM1_ADR 0x03f8 /* Serial port com1 of PC97307*/
#define NS_COM2_ADR 0x02f8 /* Serial port com2 of PC97307*/
#define NS_COM1_BASE_ADR_DYN (ISA_MSTR_IO_LOCAL + NS_COM1_ADR)
#define NS_COM2_BASE_ADR_DYN (ISA_MSTR_IO_LOCAL + NS_COM2_ADR)
/* serial ports (COM) */
/*#define PMC_COM_ADR 0xff900000*//*0xFFF80008*/
#define PMC_COM_ADR (MPC8240_EUMB_BASE + 0x4500)
#define COM1_BASE_ADR PMC_COM_ADR /* serial port 1 */
#define PMC_COM_SIZE 0x00001000
/* PC97307 UART1&2 added by xdg, 00.10.16*/
#define COM2_BASE_ADR (MPC8240_EUMB_BASE + 0x4600) /* serial port 2 */ /* modified by zoutl 2003-3-28 17:32 */
#define COM3_BASE_ADR NS_COM2_BASE_ADR_DYN /* serial port 3 */
#define UART_REG_ADDR_INTERVAL 1 /* addr differential */
#define N_UART_CHANNELS 1 /* No. serial I/O chans should be 3, xdg */ /* uart2 */
#define N_SIO_CHANNELS N_UART_CHANNELS /* No. serial I/O chans */
#define NV_RAM_READ(x) sysNvRead (x)
#define NV_RAM_WRITE(x,y) sysNvWrite (x,y)
/* Dec2155x (Drawbridge) related defines */
#define DEC2155X_MAILBOX_INT_VEC (DEC2155X_DOORBELL0_INT_VEC + \
DEC2155X_SM_DOORBELL_BIT)
#ifdef INCLUDE_DEC2155X
# define DEC2155X_BIST_VAL 0x00
# define DEC2155X_PRI_PRG_IF_VAL 0x00
# define DEC2155X_PRI_SUBCLASS_VAL 0x20
# define DEC2155X_PRI_CLASS_VAL 0x0b
# define DEC2155X_SEC_PRG_IF_VAL 0x00
# define DEC2155X_SEC_SUBCLASS_VAL 0x80
# define DEC2155X_SEC_CLASS_VAL 0x06
# define DEC2155X_MAX_LAT_VAL 0x00
# define DEC2155X_MIN_GNT_VAL 0xff
# define DEC2155X_CHP_CTRL0_VAL 0x0000
# define DEC2155X_CHP_CTRL1_VAL 0x0000
# define DEC2155X_PRI_SERR_VAL (DEC2155X_SERR_DIS_DLYD_TRNS_MSTR_ABRT | \
DEC2155X_SERR_DIS_DLYD_RD_TRNS_TO | \
DEC2155X_SERR_DIS_DLYD_WRT_TRNS_DISC | \
DEC2155X_SERR_DIS_PSTD_WRT_DATA_DISC | \
DEC2155X_SERR_DIS_PSTD_WRT_TRGT_ABRT | \
DEC2155X_SERR_DIS_PSTD_WRT_MSTR_ABRT | \
DEC2155X_SERR_DIS_PSTD_WRT_PAR_ERROR)
# define DEC2155X_SEC_SERR_VAL (DEC2155X_SERR_DIS_DLYD_TRNS_MSTR_ABRT | \
DEC2155X_SERR_DIS_DLYD_RD_TRNS_TO | \
DEC2155X_SERR_DIS_DLYD_WRT_TRNS_DISC | \
DEC2155X_SERR_DIS_PSTD_WRT_DATA_DISC | \
DEC2155X_SERR_DIS_PSTD_WRT_TRGT_ABRT | \
DEC2155X_SERR_DIS_PSTD_WRT_MSTR_ABRT | \
DEC2155X_SERR_DIS_PSTD_WRT_PAR_ERROR)
#endif /* INCLUDE_DEC2155X */
/* INTERRUPT DEFINES */
#define INT_VEC_IRQ0 0x00 /* vector for IRQ0 */
#define INT_NUM_IRQ0 INT_VEC_IRQ0
#define TIMER_INTERRUPT_BASE 0x00
#define EXTERNAL_INTERRUPT_BASE 0x10
#define INTERNAL_INTERRUPT_BASE 0x20
#define SERIAL_INTERRUPT_BASE 0x30
#define DUART_INTERRUPT_BASE 0x40
/*#define USER1_INTERRUPT_BASE 0x40*/
#define USER2_INTERRUPT_BASE 0x50
#define DEC2155X_INTERRUPT_BASE 0x60
#define USER3_INTERRUPT_BASE 0x70
#define WBPIC_INTERRUPT_BASE 0x80 /*add for WinBond, xdg*/
/* interrupt Level definitions */
/* EPIC Timers */
/* EPIC timer 0 interrupt level */
#define TIMER0_INT_LVL ( 0x0 + TIMER_INTERRUPT_BASE )
/* EPIC timer 1 interrupt level */
#define TIMER1_INT_LVL ( 0x1 + TIMER_INTERRUPT_BASE )
/* EPIC timer 2 interrupt level */
#define TIMER2_INT_LVL ( 0x2 + TIMER_INTERRUPT_BASE )
/* EPIC timer 3 interrupt level */
#define TIMER3_INT_LVL ( 0x3 + TIMER_INTERRUPT_BASE )
#if(0)
/* External interrupt sources */
/* PCI expansion INTA */
#define PMC_INTA_LVL ( 0x07 + SERIAL_INTERRUPT_BASE )
/* PCI expansion INTB */
#define PMC_INTB_LVL ( 0x08 + SERIAL_INTERRUPT_BASE )
/* ethernet interrupt level */
#define LN_INT_LVL ( 0x08 + SERIAL_INTERRUPT_BASE )
/* PCI expansion INTC */
#define PMC_INTC_LVL ( 0x09 + SERIAL_INTERRUPT_BASE )
/* PCI expansion INTD */
#define PMC_INTD_LVL ( 0x0a + SERIAL_INTERRUPT_BASE )
/* 16550 UART interrupt level (COM port 1) */
#define COM1_INT_LVL ( 0x0d + SERIAL_INTERRUPT_BASE )
/* front panel abort switch */
#define ABORT_INT_LVL ( 0x0e + SERIAL_INTERRUPT_BASE )
#endif
#define EPIC_IRQ0_LVL ( 0x0 + EXTERNAL_INTERRUPT_BASE)
#define EPIC_IRQ1_LVL ( 0x1 + EXTERNAL_INTERRUPT_BASE)
#define EPIC_IRQ2_LVL ( 0x2 + EXTERNAL_INTERRUPT_BASE)
#define EPIC_IRQ3_LVL ( 0x3 + EXTERNAL_INTERRUPT_BASE)
#define EPIC_IRQ4_LVL ( 0x4 + EXTERNAL_INTERRUPT_BASE)
#define PMC_INTA_LVL EPIC_IRQ0_LVL
#define PMC_INTB_LVL EPIC_IRQ1_LVL
#define PMC_INTC_LVL EPIC_IRQ2_LVL
#define PMC_INTD_LVL EPIC_IRQ3_LVL
/* 16550 UART interrupt level (COM port 1) */
/*#define COM1_INT_LVL EPIC_IRQ4_LVL*/
/* EPIC internal interrupts */
/* Mpc8240 I2C interrupt */
#define I2C_INT_LVL (0x00 + INTERNAL_INTERRUPT_BASE )
/* EPIC DMA #0 */
#define DMA0_INT_LVL (0x01 + INTERNAL_INTERRUPT_BASE )
/* EPIC DMA #1 */
#define DMA1_INT_LVL (0x02 + INTERNAL_INTERRUPT_BASE )
/* Message Unit interrupt*/
#define MSGUNIT_INT_LVL (0x03 + INTERNAL_INTERRUPT_BASE )
#define DUART1_INT_LVL (0x00 + DUART_INTERRUPT_BASE)
#define DUART2_INT_LVL (0x01 + DUART_INTERRUPT_BASE)
/* 16550 UART interrupt level (COM port 1) */
#define COM1_INT_LVL DUART1_INT_LVL
#define COM2_INT_LVL DUART2_INT_LVL /* add by zoutl for use two UART 2003-3-28 17:27 */
#define DEC2155X_DOORBELL0_INT_LVL ( 0x00 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL1_INT_LVL ( 0x01 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL2_INT_LVL ( 0x02 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL3_INT_LVL ( 0x03 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL4_INT_LVL ( 0x04 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL5_INT_LVL ( 0x05 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL6_INT_LVL ( 0x06 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL7_INT_LVL ( 0x07 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL8_INT_LVL ( 0x08 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL9_INT_LVL ( 0x09 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL10_INT_LVL ( 0x0a + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL11_INT_LVL ( 0x0b + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL12_INT_LVL ( 0x0c + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL13_INT_LVL ( 0x0d + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL14_INT_LVL ( 0x0e + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL15_INT_LVL ( 0x0f + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_PWR_MGMT_INT_LVL ( 0x10 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_I2O_INT_LVL ( 0x11 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_PG_CRSSNG_INT_LVL ( 0x12 + DEC2155X_INTERRUPT_BASE )
/* Winbond 83c553 PIC interrupt level define. added by xdg 00.10.12*/
#define WBPIC_IRQ0_INT_LVL ( 0x00 + WBPIC_INTERRUPT_BASE )
#define WBPIC_IRQ1_INT_LVL ( 0x01 + WBPIC_INTERRUPT_BASE )
#define WBPIC_IRQ2_INT_LVL ( 0x02 + WBPIC_INTERRUPT_BASE )
#define WBPIC_IRQ3_INT_LVL ( 0x03 + WBPIC_INTERRUPT_BASE )
#define WBPIC_IRQ4_INT_LVL ( 0x04 + WBPIC_INTERRUPT_BASE )
#define WBPIC_IRQ5_INT_LVL ( 0x05 + WBPIC_INTERRUPT_BASE )
#define WBPIC_IRQ6_INT_LVL ( 0x06 + WBPIC_INTERRUPT_BASE )
#define WBPIC_IRQ7_INT_LVL ( 0x07 + WBPIC_INTERRUPT_BASE )
#define WBPIC_IRQ8_INT_LVL ( 0x08 + WBPIC_INTERRUPT_BASE )
#define WBPIC_IRQ9_INT_LVL ( 0x09 + WBPIC_INTERRUPT_BASE )
#define WBPIC_IRQ10_INT_LVL ( 0x0a + WBPIC_INTERRUPT_BASE )
#define WBPIC_IRQ11_INT_LVL ( 0x0b + WBPIC_INTERRUPT_BASE )
#define WBPIC_IRQ12_INT_LVL ( 0x0c + WBPIC_INTERRUPT_BASE )
#define WBPIC_IRQ13_INT_LVL ( 0x0d + WBPIC_INTERRUPT_BASE )
#define WBPIC_IRQ14_INT_LVL ( 0x0e + WBPIC_INTERRUPT_BASE )
#define WBPIC_IRQ15_INT_LVL ( 0x0f + WBPIC_INTERRUPT_BASE )
/* interrupt vector definitions */
/* PRPMC600 interrupt vector definitions */
#define LN_INT_VEC INT_VEC_IRQ0 + LN_INT_LVL
#define EPIC_IRQ0_VEC INT_VEC_IRQ0 + EPIC_IRQ0_LVL
#define EPIC_IRQ1_VEC INT_VEC_IRQ0 + EPIC_IRQ1_LVL
#define EPIC_IRQ2_VEC INT_VEC_IRQ0 + EPIC_IRQ2_LVL
#define EPIC_IRQ3_VEC INT_VEC_IRQ0 + EPIC_IRQ3_LVL
#define EPIC_IRQ4_VEC INT_VEC_IRQ0 + EPIC_IRQ4_LVL
#define PMC_INTA_VEC INT_VEC_IRQ0 + PMC_INTA_LVL
#define PMC_INTB_VEC INT_VEC_IRQ0 + PMC_INTB_LVL
#define PMC_INTC_VEC INT_VEC_IRQ0 + PMC_INTC_LVL
#define PMC_INTD_VEC INT_VEC_IRQ0 + PMC_INTD_LVL
/*for pmc 16552 uart*/
#define COM1_INT_VEC COM1_INT_LVL/*EPIC_IRQ4_VEC*/
#define COM2_INT_VEC COM2_INT_LVL /* add by zoutl for use two UART 2003-3-28 17:27 */
#define ABORT_INT_VEC INT_VEC_IRQ0 + ABORT_INT_LVL
#define TIMER0_INT_VEC INT_VEC_IRQ0 + TIMER0_INT_LVL
#define TIMER1_INT_VEC INT_VEC_IRQ0 + TIMER1_INT_LVL
#define TIMER2_INT_VEC INT_VEC_IRQ0 + TIMER2_INT_LVL
#define TIMER3_INT_VEC INT_VEC_IRQ0 + TIMER3_INT_LVL
#define DEC2155X_DOORBELL0_INT_VEC (INT_VEC_IRQ0 + DEC2155X_DOORBELL0_INT_LVL)
#define DEC2155X_DOORBELL1_INT_VEC (INT_VEC_IRQ0 + DEC2155X_DOORBELL1_INT_LVL)
#define DEC2155X_DOORBELL2_INT_VEC (INT_VEC_IRQ0 + DEC2155X_DOORBELL2_INT_LVL)
#define DEC2155X_DOORBELL3_INT_VEC (INT_VEC_IRQ0 + DEC2155X_DOORBELL3_INT_LVL)
#define DEC2155X_DOORBELL4_INT_VEC (INT_VEC_IRQ0 + DEC2155X_DOORBELL4_INT_LVL)
#define DEC2155X_DOORBELL5_INT_VEC (INT_VEC_IRQ0 + DEC2155X_DOORBELL5_INT_LVL)
#define DEC2155X_DOORBELL6_INT_VEC (INT_VEC_IRQ0 + DEC2155X_DOORBELL6_INT_LVL)
#define DEC2155X_DOORBELL7_INT_VEC (INT_VEC_IRQ0 + DEC2155X_DOORBELL7_INT_LVL)
#define DEC2155X_DOORBELL8_INT_VEC (INT_VEC_IRQ0 + DEC2155X_DOORBELL8_INT_LVL)
#define DEC2155X_DOORBELL9_INT_VEC (INT_VEC_IRQ0 + DEC2155X_DOORBELL9_INT_LVL)
#define DEC2155X_DOORBELL10_INT_VEC (INT_VEC_IRQ0 + DEC2155X_DOORBELL10_INT_LVL)
#define DEC2155X_DOORBELL11_INT_VEC (INT_VEC_IRQ0 + DEC2155X_DOORBELL11_INT_LVL)
#define DEC2155X_DOORBELL12_INT_VEC (INT_VEC_IRQ0 + DEC2155X_DOORBELL12_INT_LVL)
#define DEC2155X_DOORBELL13_INT_VEC (INT_VEC_IRQ0 + DEC2155X_DOORBELL13_INT_LVL)
#define DEC2155X_DOORBELL14_INT_VEC (INT_VEC_IRQ0 + DEC2155X_DOORBELL14_INT_LVL)
#define DEC2155X_DOORBELL15_INT_VEC (INT_VEC_IRQ0 + DEC2155X_DOORBELL15_INT_LVL)
#define DEC2155X_PWR_MGMT_INT_VEC (INT_VEC_IRQ0 + DEC2155X_PWR_MGMT_INT_LVL)
#define DEC2155X_I2O_INT_VEC (INT_VEC_IRQ0 + DEC2155X_I2O_INT_LVL)
#define DEC2155X_PG_CRSSNG_INT_VEC (INT_VEC_IRQ0 + DEC2155X_PG_CRSSNG_INT_LVL)
/* Winbond 83C553 PIC interrupt vector define. added by xdg,00.10.12 */
#define WBPIC_IRQ0_INT_VEC (INT_VEC_IRQ0 + WBPIC_IRQ0_INT_LVL)
#define WBPIC_IRQ1_INT_VEC (INT_VEC_IRQ0 + WBPIC_IRQ1_INT_LVL)
#define WBPIC_IRQ2_INT_VEC (INT_VEC_IRQ0 + WBPIC_IRQ2_INT_LVL)
#define WBPIC_IRQ3_INT_VEC (INT_VEC_IRQ0 + WBPIC_IRQ3_INT_LVL)
#define WBPIC_IRQ4_INT_VEC (INT_VEC_IRQ0 + WBPIC_IRQ4_INT_LVL)
#define WBPIC_IRQ5_INT_VEC (INT_VEC_IRQ0 + WBPIC_IRQ5_INT_LVL)
#define WBPIC_IRQ6_INT_VEC (INT_VEC_IRQ0 + WBPIC_IRQ6_INT_LVL)
#define WBPIC_IRQ7_INT_VEC (INT_VEC_IRQ0 + WBPIC_IRQ7_INT_LVL)
#define WBPIC_IRQ8_INT_VEC (INT_VEC_IRQ0 + WBPIC_IRQ8_INT_LVL)
#define WBPIC_IRQ9_INT_VEC (INT_VEC_IRQ0 + WBPIC_IRQ9_INT_LVL)
#define WBPIC_IRQ10_INT_VEC (INT_VEC_IRQ0 + WBPIC_IRQ10_INT_LVL)
#define WBPIC_IRQ11_INT_VEC (INT_VEC_IRQ0 + WBPIC_IRQ11_INT_LVL)
#define WBPIC_IRQ12_INT_VEC (INT_VEC_IRQ0 + WBPIC_IRQ12_INT_LVL)
#define WBPIC_IRQ13_INT_VEC (INT_VEC_IRQ0 + WBPIC_IRQ13_INT_LVL)
#define WBPIC_IRQ14_INT_VEC (INT_VEC_IRQ0 + WBPIC_IRQ14_INT_LVL)
#define WBPIC_IRQ15_INT_VEC (INT_VEC_IRQ0 + WBPIC_IRQ15_INT_LVL)
#define WBPIC_IRQ PMC_INTC_LVL
/* PC97307 serial interrupt define, xdg */
#define NS_COM1_INT_LVL WBPIC_IRQ4_INT_LVL /* com1 interrupt level of PC97307 */
#define NS_COM2_INT_LVL WBPIC_IRQ3_INT_LVL /* com2 interrupt level of PC97307 */
#define NS_COM1_INT_VEC WBPIC_IRQ4_INT_VEC
#define NS_COM2_INT_VEC WBPIC_IRQ3_INT_VEC
/* #define COM2_INT_LVL NS_COM1_INT_LVL */ /* mask by zoutl 2003-4-1 14:37 */
#define COM3_INT_LVL NS_COM2_INT_LVL
/* #define COM2_INT_VEC NS_COM1_INT_VEC */ /* mask by zoutl 2003-4-1 14:37 */
#define COM3_INT_VEC NS_COM2_INT_VEC
#define PCI_8139_INT_VEC PMC_INTD_LVL
/*
* Address range definitions for PCI bus.
*
* Used with vxMemProbe() hook sysBusProbe().
*/
#define IS_PCI_ADDRESS(adrs) \
((((UINT32)(adrs) >= (UINT32)PCI_MSTR_MEM_LO_ADRS) && \
((UINT32)(adrs) < (UINT32)PCI_MSTR_MEM_HI_ADRS)) || \
(((UINT32)(adrs) >= (UINT32)PCI_MSTR_IO_LO_ADRS) && \
((UINT32)(adrs) < (UINT32)PCI_MSTR_IO_HI_ADRS)))
/* PCI bus number for primary PCI bus */
#define PCI_PRIMARY_BUS 0
#ifndef _ASMLANGUAGE
# ifdef SYS_SM_ANCHOR_POLL_LIST
/* Shared memory anchor polling list */
typedef struct sysSmAnchorPollingList
{
UINT devVend;
UINT subIdVend;
} SYS_SM_ANCHOR_POLLING_LIST;
# endif
/*
* Shared memory device list
*/
typedef struct sysSmDevList
{
UINT devVend;
UINT subIdVend;
} SYS_SM_DEV_LIST;
#endif /* ifndef _ASMLANGUAGE */
/*
* Support for determining if we're ROM based or not. _sysInit
* saves the startType parameter at location ROM_BASED_FLAG.
*/
#define PCI_AUTOCONFIG_FLAG_OFFSET ( 0x4c00 )
#define PCI_AUTOCONFIG_FLAG ( *(UCHAR *)(LOCAL_MEM_LOCAL_ADRS + \
PCI_AUTOCONFIG_FLAG_OFFSET) )
#define PCI_AUTOCONFIG_DONE ( PCI_AUTOCONFIG_FLAG != 0 )
#ifdef __cplusplus
}
#endif
#endif /* INCprpmc600h */