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/* mpc8240.h - Mpc8240 chip header file */
/* Copyright 1984-2000 Wind River Systems, Inc. */
/* Copyright 1996-2000 Motorola, Inc. All Rights Reserved */
/*
modification history
--------------------
01a,25feb00,rhk created from version 01f, mv2100 BSP.
*/
/*
This file contains Base address defines, register offsets and bit
definitions for the the Mpc8240 chip
*/
#ifndef INCmpc8240h
#define INCmpc8240h
#ifdef __cplusplus
extern "C" {
#endif
#ifdef _ASMLANGUAGE
#define CAST(x)
#else
typedef volatile UINT32 VUINT32; /* volatile unsigned word */
typedef volatile UINT16 VUINT16; /* volatile unsigned halfword */
typedef volatile UINT8 VUINT8; /* volatile unsigned byte */
#define CAST(x) (x)
#endif /* _ASMLANGUAGE */
/*
* IBC Extensions to Standard PCI Config Header register offsets
*/
#define PCI_CFG_IBC_INTR_ROUTE 0x44
#define PCI_CFG_IBC_ARB_CTL 0x83
/* PCI Arbiter Control Register bit definitions */
#define ARB_CTL_GAT (1 << 7)
#define ARB_CTL_TIMEOUT_TIMER (1 << 2)
#define ARB_CTL_BUS_LOCK (1 << 0)
/* Aux Clock Legacy */
#define DESTINATION_CPU0 0x00000001
/* Mpc8240 Base addresses */
#define MPC8240_EUMB_SIZE 0x00100000
#define MPC8240_EUMB_BASE MPC8240_REGISTERS_BASE
#define MPC8240_PCSR_BASE 0x9a000000
/*
* Base addresses for the compnents of the Embedded Utilities Memory
* Block. These form the base addresses for the bulk of the Mpc8240
* registers and are offset from the MPC8240_EMBEDDED_UTILS_MEM_BLOCK_BASE
*/
#define MPC8240_I2O_BASE (MPC8240_EUMB_BASE + 0x00000)
#define MPC8240_DMA_BASE (MPC8240_EUMB_BASE + 0x01000)
#define MPC8240_ATU_BASE (MPC8240_EUMB_BASE + 0x02000)
#define MPC8240_I2C_BASE (MPC8240_EUMB_BASE + 0x03000)
#define MPC8240_EPIC_BASE (MPC8240_EUMB_BASE + 0x40000)
#define MPC8240_DIAG_REGS_BASE (MPC8240_EUMB_BASE + 0x80000)
#define EPIC_BASE MPC8240_EPIC_BASE
#define DIAG_BASE MPC8240_DIAG_REGS_BASE
/* hardware implementation register extensions for Mpc8240 */
#define HID2 1011 /* HID2 is SPR 1011 */
/*
* HID0 bit modifications for the Mpc8240
* The original bit definitions for HID0 are in arch/ppc/ppc603.h
*/
#undef _PPC_HID0_EICE /* not used in 603e CPUs */
#undef _PPC_HID0_SIED /* not used in 603e CPUs */
#undef _PPC_HID0_BHTE /* not used in 603e CPUs */
#define _PPC_HID0_IFEM 0x00000080 /* instruction fetch enable M bit */
#define _PPC_HID0_FBIOB 0x00000010 /* force branch indirect on bus */
#define _PPC_HID0_ABE 0x00000008 /* address broadcast enable */
#define _PPC_HID0_NOOPTI 0x00000001 /* NO-OP touch instructions */
/* HID1 bit definitions */
#define _PPC_HID1_PC0 0x80000000 /* PLL config bit 0 (read only) */
#define _PPC_HID1_PC1 0x40000000 /* PLL config bit 1 (read only) */
#define _PPC_HID1_PC2 0x20000000 /* PLL config bit 2 (read only) */
#define _PPC_HID1_PC3 0x10000000 /* PLL config bit 3 (read only) */
#define _PPC_HID1_PC4 0x08000000 /* PLL config bit 4 (read only) */
#define _PPC_HID1_FPD 0x00000001 /* floating point disabled */
/* HID2 bit definitions */
#define _PPC_HID2_SFP 0x00010000 /* speed for power */
#define _PPC_HID2_IWLCK_MASK 0x0000e000 /* instr cache way lock bits */
#define _PPC_HID2_IWLCK_SHFT 15
#define _PPC_HID2_DWLCK_MASK 0x000000e0 /* data cache way lock bits */
#define _PPC_HID2_DWLCK_SHFT 7
/* Mpc8240 Message Unit (I2O) Registers */
#define MPC8240_I2O_PIC (CAST(VUINT8 *) (MPC8240_I2O_BASE + 0x0009))
#define MPC8240_I2O_SUB_CLASS (CAST(VUINT8 *) (MPC8240_I2O_BASE + 0x000a))
#define MPC8240_I2O_BASE_CLASS (CAST(VUINT8 *) (MPC8240_I2O_BASE + 0x000b))
#define MPC8240_I2O_IMR0 (CAST(VUINT32 *) (MPC8240_I2O_BASE + 0x0050))
#define MPC8240_I2O_IMR1 (CAST(VUINT32 *) (MPC8240_I2O_BASE + 0x0054))
#define MPC8240_I2O_OMR0 (CAST(VUINT32 *) (MPC8240_I2O_BASE + 0x0058))
#define MPC8240_I2O_OMR1 (CAST(VUINT32 *) (MPC8240_I2O_BASE + 0x005c))
#define MPC8240_I2O_ODBR (CAST(VUINT32 *) (MPC8240_I2O_BASE + 0x0060))
#define MPC8240_I2O_IDBR (CAST(VUINT32 *) (MPC8240_I2O_BASE + 0x0068))
#define MPC8240_I2O_IMISR (CAST(VUINT32 *) (MPC8240_I2O_BASE + 0x0100))
#define MPC8240_I2O_IMMR (CAST(VUINT32 *) (MPC8240_I2O_BASE + 0x0104))
#define MPC8240_I2O_IFHPR (CAST(VUINT32 *) (MPC8240_I2O_BASE + 0x0120))
#define MPC8240_I2O_IFTPR (CAST(VUINT32 *) (MPC8240_I2O_BASE + 0x0128))
#define MPC8240_I2O_IPHPR (CAST(VUINT32 *) (MPC8240_I2O_BASE + 0x0130))
#define MPC8240_I2O_IPTPR (CAST(VUINT32 *) (MPC8240_I2O_BASE + 0x0138))
#define MPC8240_I2O_OFHPR (CAST(VUINT32 *) (MPC8240_I2O_BASE + 0x0140))
#define MPC8240_I2O_OFTPR (CAST(VUINT32 *) (MPC8240_I2O_BASE + 0x0148))
#define MPC8240_I2O_OPHPR (CAST(VUINT32 *) (MPC8240_I2O_BASE + 0x0150))
#define MPC8240_I2O_OPTPR (CAST(VUINT32 *) (MPC8240_I2O_BASE + 0x0158))
#define MPC8240_I2O_MUCR (CAST(VUINT32 *) (MPC8240_I2O_BASE + 0x0164))
#define MPC8240_I2O_QBAR (CAST(VUINT32 *) (MPC8240_I2O_BASE + 0x0170))
/* Mpc8240 DMA Registers */
#define MPC8240_DMA_0_MODE (CAST(VUINT32 *) (MPC8240_DMA_BASE + 0x0100))
#define MPC8240_DMA_0_STATUS (CAST(VUINT32 *) (MPC8240_DMA_BASE + 0x0104))
#define MPC8240_DMA_0_ADR_DESC (CAST(VUINT32 *) (MPC8240_DMA_BASE + 0x0108))
#define MPC8240_DMA_0_SRC_ADR (CAST(VUINT32 *) (MPC8240_DMA_BASE + 0x0110))
#define MPC8240_DMA_0_DEST_ADR (CAST(VUINT32 *) (MPC8240_DMA_BASE + 0x0118))
#define MPC8240_DMA_0_BYTE_CNT (CAST(VUINT32 *) (MPC8240_DMA_BASE + 0x0120))
#define MPC8240_DMA_0_NSER_ADR (CAST(VUINT32 *) (MPC8240_DMA_BASE + 0x0124))
#define MPC8240_DMA_1_MODE (CAST(VUINT32 *) (MPC8240_DMA_BASE + 0x0200))
#define MPC8240_DMA_1_STATUS (CAST(VUINT32 *) (MPC8240_DMA_BASE + 0x0204))
#define MPC8240_DMA_1_ADR_DESC (CAST(VUINT32 *) (MPC8240_DMA_BASE + 0x0208))
#define MPC8240_DMA_1_SRC_ADR (CAST(VUINT32 *) (MPC8240_DMA_BASE + 0x0210))
#define MPC8240_DMA_1_DEST_ADR (CAST(VUINT32 *) (MPC8240_DMA_BASE + 0x0218))
#define MPC8240_DMA_1_BYTE_CNT (CAST(VUINT32 *) (MPC8240_DMA_BASE + 0x0220))
#define MPC8240_DMA_1_NSER_ADR (CAST(VUINT32 *) (MPC8240_DMA_BASE + 0x0224))
/* Mpc8240 Address Tranlation Unit (ATU) Registers */
#define MPC8240_ATU_OMBAR (CAST(VUINT32 *) (MPC8240_ATU_BASE + 0x0300))
#define MPC8240_ATU_OTWR (CAST(VUINT32 *) (MPC8240_ATU_BASE + 0x0308))
#define MPC8240_ATU_ITWR (CAST(VUINT32 *) (MPC8240_ATU_BASE + 0x0310))
/* Mpc8240 I2C Registers */
#define MPC8240_I2C_ADR_REG (CAST(VUINT32 *) (MPC8240_I2C_BASE + 0x0000))
#define MPC8240_I2C_FREQ_DIV_REG (CAST(VUINT32 *) (MPC8240_I2C_BASE + 0x0004))
#define MPC8240_I2C_CONTROL_REG (CAST(VUINT32 *) (MPC8240_I2C_BASE + 0x0008))
#define MPC8240_I2C_STATUS_REG (CAST(VUINT32 *) (MPC8240_I2C_BASE + 0x000c))
#define MPC8240_I2C_DATA_REG (CAST(VUINT32 *) (MPC8240_I2C_BASE + 0x0010))
/* Mpc8240 EPIC Registers */
#define EPIC_FEATURE_REG (CAST(VUINT32 *) (EPIC_BASE + 0x01000))
#define EPIC_GLOBAL_CONFIG_REG (CAST(VUINT32 *) (EPIC_BASE + 0x01020))
#define EPIC_INTR_CONFIG_REG (CAST(VUINT32 *) (EPIC_BASE + 0x01030))
#define EPIC_VENDOR_ID_REG (CAST(VUINT32 *) (EPIC_BASE + 0x01080))
#define EPIC_PROCESSOR_INIT_REG (CAST(VUINT32 *) (EPIC_BASE + 0x01090))
#define EPIC_SPUR_VEC_REG (CAST(VUINT32 *) (EPIC_BASE + 0x010e0))
#define EPIC_TIMER_FREQ_REG (CAST(VUINT32 *)(EPIC_BASE + 0x010f0))
#define EPIC_TIMER0_CUR_CNT_REG (CAST(VUINT32 *) (EPIC_BASE + 0x01100))
#define EPIC_TIMER0_BASE_CT_REG (CAST(VUINT32 *) (EPIC_BASE + 0x01110))
#define EPIC_TIMER0_VEC_PRI_REG (CAST(VUINT32 *) (EPIC_BASE + 0x01120))
#define EPIC_TIMER0_DEST_REG (CAST(VUINT32 *) (EPIC_BASE + 0x01130))
#define EPIC_TIMER1_CUR_CNT_REG (CAST(VUINT32 *) (EPIC_BASE + 0x01140))
#define EPIC_TIMER1_BASE_CT_REG (CAST(VUINT32 *) (EPIC_BASE + 0x01150))
#define EPIC_TIMER1_VEC_PRI_REG (CAST(VUINT32 *) (EPIC_BASE + 0x01160))
#define EPIC_TIMER1_DEST_REG (CAST(VUINT32 *) (EPIC_BASE + 0x01170))
#define EPIC_TIMER2_CUR_CNT_REG (CAST(VUINT32 *) (EPIC_BASE + 0x01180))
#define EPIC_TIMER2_BASE_CT_REG (CAST(VUINT32 *) (EPIC_BASE + 0x01190))
#define EPIC_TIMER2_VEC_PRI_REG (CAST(VUINT32 *) (EPIC_BASE + 0x011a0))
#define EPIC_TIMER2_DEST_REG (CAST(VUINT32 *) (EPIC_BASE + 0x011b0))
#define EPIC_TIMER3_CUR_CNT_REG (CAST(VUINT32 *) (EPIC_BASE + 0x011c0))
#define EPIC_TIMER3_BASE_CT_REG (CAST(VUINT32 *) (EPIC_BASE + 0x011d0))
#define EPIC_TIMER3_VEC_PRI_REG (CAST(VUINT32 *) (EPIC_BASE + 0x011e0))
#define EPIC_TIMER3_DEST_REG (CAST(VUINT32 *) (EPIC_BASE + 0x011f0))
#define EPIC_EXT_SRC0_VEC_PRI_REG (CAST(VUINT32 *) (EPIC_BASE + 0x10200))
#define EPIC_EXT_SRC0_DEST_REG (CAST(VUINT32 *) (EPIC_BASE + 0x10210))
#define EPIC_EXT_SRC1_VEC_PRI_REG (CAST(VUINT32 *) (EPIC_BASE + 0x10220))
#define EPIC_EXT_SRC1_DEST_REG (CAST(VUINT32 *) (EPIC_BASE + 0x10230))
#define EPIC_EXT_SRC2_VEC_PRI_REG (CAST(VUINT32 *) (EPIC_BASE + 0x10240))
#define EPIC_EXT_SRC2_DEST_REG (CAST(VUINT32 *) (EPIC_BASE + 0x10250))
#define EPIC_EXT_SRC3_VEC_PRI_REG (CAST(VUINT32 *) (EPIC_BASE + 0x10260))
#define EPIC_EXT_SRC3_DEST_REG (CAST(VUINT32 *) (EPIC_BASE + 0x10270))
#define EPIC_EXT_SRC4_VEC_PRI_REG (CAST(VUINT32 *) (EPIC_BASE + 0x10280))
#define EPIC_EXT_SRC4_DEST_REG (CAST(VUINT32 *) (EPIC_BASE + 0x10290))
#define EPIC_SER_SRC0_VEC_PRI_REG (CAST(VUINT32 *) (EPIC_BASE + 0x10200))
#define EPIC_SER_SRC0_DEST_REG (CAST(VUINT32 *) (EPIC_BASE + 0x10210))
#define EPIC_SER_SRC1_VEC_PRI_REG (CAST(VUINT32 *) (EPIC_BASE + 0x10220))
#define EPIC_SER_SRC1_DEST_REG (CAST(VUINT32 *) (EPIC_BASE + 0x10230))
#define EPIC_SER_SRC2_VEC_PRI_REG (CAST(VUINT32 *) (EPIC_BASE + 0x10240))
#define EPIC_SER_SRC2_DEST_REG (CAST(VUINT32 *) (EPIC_BASE + 0x10250))
#define EPIC_SER_SRC3_VEC_PRI_REG (CAST(VUINT32 *) (EPIC_BASE + 0x10260))
#define EPIC_SER_SRC3_DEST_REG (CAST(VUINT32 *) (EPIC_BASE + 0x10270))
#define EPIC_SER_SRC4_VEC_PRI_REG (CAST(VUINT32 *) (EPIC_BASE + 0x10280))
#define EPIC_SER_SRC4_DEST_REG (CAST(VUINT32 *) (EPIC_BASE + 0x10290))
#define EPIC_SER_SRC5_VEC_PRI_REG (CAST(VUINT32 *) (EPIC_BASE + 0x102a0))
#define EPIC_SER_SRC5_DEST_REG (CAST(VUINT32 *) (EPIC_BASE + 0x102b0))
#define EPIC_SER_SRC6_VEC_PRI_REG (CAST(VUINT32 *) (EPIC_BASE + 0x102c0))
#define EPIC_SER_SRC6_DEST_REG (CAST(VUINT32 *) (EPIC_BASE + 0x102d0))
#define EPIC_SER_SRC7_VEC_PRI_REG (CAST(VUINT32 *) (EPIC_BASE + 0x102e0))
#define EPIC_SER_SRC7_DEST_REG (CAST(VUINT32 *) (EPIC_BASE + 0x102f0))
#define EPIC_SER_SRC8_VEC_PRI_REG (CAST(VUINT32 *) (EPIC_BASE + 0x10300))
#define EPIC_SER_SRC8_DEST_REG (CAST(VUINT32 *) (EPIC_BASE + 0x10310))
#define EPIC_SER_SRC9_VEC_PRI_REG (CAST(VUINT32 *) (EPIC_BASE + 0x10320))
#define EPIC_SER_SRC9_DEST_REG (CAST(VUINT32 *) (EPIC_BASE + 0x10330))
#define EPIC_SER_SRC10_VEC_PRI_REG (CAST(VUINT32 *) (EPIC_BASE + 0x10340))
#define EPIC_SER_SRC10_DEST_REG (CAST(VUINT32 *) (EPIC_BASE + 0x10350))
#define EPIC_SER_SRC11_VEC_PRI_REG (CAST(VUINT32 *) (EPIC_BASE + 0x10360))
#define EPIC_SER_SRC11_DEST_REG (CAST(VUINT32 *) (EPIC_BASE + 0x10370))
#define EPIC_SER_SRC12_VEC_PRI_REG (CAST(VUINT32 *) (EPIC_BASE + 0x10380))
#define EPIC_SER_SRC12_DEST_REG (CAST(VUINT32 *) (EPIC_BASE + 0x10390))
#define EPIC_SER_SRC13_VEC_PRI_REG (CAST(VUINT32 *) (EPIC_BASE + 0x103a0))
#define EPIC_SER_SRC13_DEST_REG (CAST(VUINT32 *) (EPIC_BASE + 0x103b0))
#define EPIC_SER_SRC14_VEC_PRI_REG (CAST(VUINT32 *) (EPIC_BASE + 0x103c0))
#define EPIC_SER_SRC14_DEST_REG (CAST(VUINT32 *) (EPIC_BASE + 0x103d0))
#define EPIC_SER_SRC15_VEC_PRI_REG (CAST(VUINT32 *) (EPIC_BASE + 0x103e0))
#define EPIC_SER_SRC15_DEST_REG (CAST(VUINT32 *) (EPIC_BASE + 0x103f0))
#define EPIC_I2C_INTR_VEC_SRC (CAST(VUINT32 *) (EPIC_BASE + 0x11020))
#define EPIC_I2C_INTR_DEST (CAST(VUINT32 *) (EPIC_BASE + 0x11030))
#define EPIC_DMA_CHAN0_INTR_VEC_SRC (CAST(VUINT32 *) (EPIC_BASE + 0x11040))
#define EPIC_DMA_CHAN0_INTR_DEST (CAST(VUINT32 *) (EPIC_BASE + 0x11050))
#define EPIC_DMA_CHAN1_INTR_VEC_SRC (CAST(VUINT32 *) (EPIC_BASE + 0x11060))
#define EPIC_DMA_CHAN1_INTR_DEST (CAST(VUINT32 *) (EPIC_BASE + 0x11070))
#define EPIC_MSG_UNIT_INTR_VEC_SRC (CAST(VUINT32 *) (EPIC_BASE + 0x110c0))
#define EPIC_MSG_UNIT_INTR_DEST (CAST(VUINT32 *) (EPIC_BASE + 0x110d0))
#define EPIC_DUART_CHAN1_INTR_VEC_SRC (CAST(VUINT32 *) (EPIC_BASE + 0x11120))
#define EPIC_DUART_CHAN1_INTR_DEST (CAST(VUINT32 *) (EPIC_BASE + 0x11130))
#define EPIC_DUART_CHAN2_INTR_VEC_SRC (CAST(VUINT32 *) (EPIC_BASE + 0x11140))
#define EPIC_DUART_CHAN2_INTR_DEST (CAST(VUINT32 *) (EPIC_BASE + 0x11150))
#define EPIC_CUR_TASK_PRI_REG (CAST(VUINT32 *) (EPIC_BASE + 0x20080))
#define EPIC_IACK_REG (CAST(VUINT32 *) (EPIC_BASE + 0x200a0))
#define EPIC_EOI_REG (CAST(VUINT32 *) (EPIC_BASE + 0x200b0))
/* Mpc8240 Diagnostic Registers */
#define MPC8240_DIAG_WP_DH_REG (CAST(VUINT32 *) (DIAG_BASE + 0x7f00c))
#define MPC8240_DIAG_WP_DL_REG (CAST(VUINT32 *) (DIAG_BASE + 0x7f010))
#define MPC8240_DIAG_WP_PAR_REG (CAST(VUINT32 *) (DIAG_BASE + 0x7f014))
#define MPC8240_DIAG_WP1_CNTL_TRIG (CAST(VUINT32 *) (DIAG_BASE + 0x7f018))
#define MPC8240_DIAG_WP1_ADDR_TRIG (CAST(VUINT32 *) (DIAG_BASE + 0x7f01c))
#define MPC8240_DIAG_WP1_CTRL_MASK (CAST(VUINT32 *) (DIAG_BASE + 0x7f020))
#define MPC8240_DIAG_WP1_ADDR_MASK (CAST(VUINT32 *) (DIAG_BASE + 0x7f024))
#define MPC8240_DIAG_WP1_CTRL_MON (CAST(VUINT32 *) (DIAG_BASE + 0x7f028))
#define MPC8240_DIAG_WP1_ADDR_MON (CAST(VUINT32 *) (DIAG_BASE + 0x7f02c))
#define MPC8240_DIAG_WP2_CNTL_TRIG (CAST(VUINT32 *) (DIAG_BASE + 0x7f030))
#define MPC8240_DIAG_WP2_ADDR_TRIG (CAST(VUINT32 *) (DIAG_BASE + 0x7f034))
#define MPC8240_DIAG_WP2_CTRL_MASK (CAST(VUINT32 *) (DIAG_BASE + 0x7f038))
#define MPC8240_DIAG_WP2_ADDR_MASK (CAST(VUINT32 *) (DIAG_BASE + 0x7f03c))
#define MPC8240_DIAG_WP2_CTRL_MON (CAST(VUINT32 *) (DIAG_BASE + 0x7f040))
#define MPC8240_DIAG_WP2_ADDR_MON (CAST(VUINT32 *) (DIAG_BASE + 0x7f044))
#define MPC8240_DIAG_WPM_CONTROL (CAST(VUINT32 *) (DIAG_BASE + 0x7f048))
/* Mpc8240 Configuration Registers */
#define MPC8240_CFG_VENDOR_ID 0x00 /* vendor ID = 0x1057 */
#define MPC8240_CFG_DEVICE_ID 0x02 /* device ID = 0x0003 */
#define MPC8240_CFG_COMMAND 0x04 /* PCI command register */
#define MPC8240_CFG_STATUS 0x06 /* PCI status register */
#define MPC8240_CFG_REVISION 0x08 /* revision identifier */
#define MPC8240_CFG_PROGRAMMING_IF 0x09 /* standard programming intf */
#define MPC8240_CFG_SUBCLASS 0x0a /* subclass code */
#define MPC8240_CFG_CLASS 0x0b /* class code */
#define MPC8240_CFG_CACHE_LINE_SIZE 0x0c /* cache line size */
#define MPC8240_CFG_LATENCY_TIMER 0x0d /* latency timer */
#define MPC8240_CFG_HEADER_TYPE 0x0e /* header type */
#define MPC8240_CFG_BIST 0x0f /* BIST control */
#define MPC8240_CFG_DEV_INT_LINE 0x3c /* interrupt line */
#define MPC8240_CFG_DEV_INT_PIN 0x3d /* interrupt pin */
#define MPC8240_CFG_MIN_GRANT 0x3e /* minimum grant */
#define MPC8240_CFG_MAX_LATENCY 0x3f /* maximum latency */
#define MPC8240_CFG_PCI_ARBITER_CNTL 0x46 /* PCI arbiter control */
#define MPC8240_CFG_PERF_MON_CMND_REG 0x48 /* performance mon command */
#define MPC8240_CFG_PERF_MON_CNTL_REG 0x4c /* perf monitor mode ctl */
#define MPC8240_CFG_PERF_MON_COUNTER0 0x50 /* perf monitor counter 0 */
#define MPC8240_CFG_PERF_MON_COUNTER1 0x54 /* perf monitor counter 1 */
#define MPC8240_CFG_PERF_MON_COUNTER2 0x58 /* perf monitor counter 2 */
#define MPC8240_CFG_PERF_MON_COUNTER3 0x5c /* perf monitor counter 3 */
#define MPC8240_CFG_PWR_MGT_CFG_REG 0x70 /* power mgmnt config */
#define MPC8240_CFG_PWR_MGT_CFG_REG2 0x72 /* power mgmnt config 2 */
#define MPC8240_CFG_OUTPUT_DRIVER_REG 0x73 /* output driver control */
#define MPC8240_CFG_CLOCK_DRIVER_REG 0x74 /* clock driver control */
#define MPC8240_CFG_EUMBBAR 0x78 /* Embedded Utils base addr */
#define MPC8240_CFG_MEM_STRT_ADR_REG 0x80 /* memory starting address */
#define MPC8240_CFG_MEM_STRT_UADR_REG 0x84 /* memory starting address up */
#define MPC8240_CFG_EXT_MEM_STRT_ADR_REG 0x88 /* ext. mem start addr */
#define MPC8240_CFG_EXT_MEM_ST_UADR_REG 0x8c /* ext. mem start addr upper*/
#define MPC8240_CFG_MEM_END_ADR_REG 0x90 /* memory ending address */
#define MPC8240_CFG_MEM_END_UADR_REG 0x94 /* memory ending address upr */
#define MPC8240_CFG_EXT_MEM_END_ADR_REG 0x98 /* ext. mem ending addr */
#define MPC8240_CFG_EXT_MEM_END_UADR_REG 0x9c /* ext. mem ending addr upper */
#define MPC8240_CFG_MEM_BANK_ENABLE_REG 0xa0 /* memory bank enable */
#define MPC8240_CFG_PAGE_MODE_CTR_TIMER 0xa3 /* page mode counter/timer */
#define MPC8240_CFG_PROC_IF_CFG1 0xa8 /* processor interface config */
#define MPC8240_CFG_PROC_IF_CFG2 0xac /* processor interf config 2 */
#define MPC8240_CFG_ECC_ERROR_CTR 0xb8 /* ECC single bit err counter */
#define MPC8240_CFG_ECC_ERROR_TRIG 0xb9 /* ECC single bit err trigger */
#define MPC8240_CFG_ERROR_ENABLE1 0xc0 /* error enable 1 */
#define MPC8240_CFG_ERROR_DETECT1 0xc1 /* error detect 1 */
#define MPC8240_CFG_CPU_BUS_ERR_STAT 0xc3 /* CPU bus error status */
#define MPC8240_CFG_ERROR_ENABLE2 0xc4 /* error enable 2 */
#define MPC8240_CFG_ERROR_DETECT2 0xc5 /* error detect 2 */
#define MPC8240_CFG_PCI_BUS_ERR_STAT 0xc7 /* PCI bus error status */
#define MPC8240_CFG_CPU_PCI_ERR_ADR 0xc8 /* CPU/PCI bus error address */
#define MPC8240_CFG_MISC_REG1 0xe0 /* emulation support config */
#define MPC8240_CFG_MEM_CNTL_CFG_REG1 0xf0 /* memory control config 1 */
#define MPC8240_CFG_MEM_CNTL_CFG_REG2 0xf4 /* memory control config 2 */
#define MPC8240_CFG_MEM_CNTL_CFG_REG3 0xf8 /* memory control config 3 */
#define MPC8240_CFG_MEM_CNTL_CFG_REG4 0xfc /* memory control config 4 */
/* Mpc8240 Configuration registers accessible from the PCI bus */
#define MPC8240_CFG_LMBAR 0x10 /* local mem base addr reg */
#define MPC8240_CFG_PCSRBAR 0x14 /* periph ctrl/stat base adr */
/* Mpc8240 Configuration Register Bit Definitions */
/* Offset 0x04 - Mpc8240 Command Register Bits */
#define MPC8240_CMD_IO_ENABLE 0x0001 /* IO access enable */
#define MPC8240_CMD_MEM_ENABLE 0x0002 /* memory access enable */
#define MPC8240_CMD_MASTER_ENABLE 0x0004 /* bus master enable */
#define MPC8240_CMD_MON_ENABLE 0x0008 /* monitor special cycles enable */
#define MPC8240_CMD_WI_ENABLE 0x0010 /* write and invalidate enable */
#define MPC8240_CMD_SNOOP_ENABLE 0x0020 /* palette snoop enable */
#define MPC8240_CMD_PERR_ENABLE 0x0040 /* parity error enable */
#define MPC8240_CMD_WC_ENABLE 0x0080 /* wait cycle enable */
#define MPC8240_CMD_SERR_ENABLE 0x0100 /* system error enable */
#define MPC8240_CMD_FBTB_ENABLE 0x0200 /* fast back to back enable */
/* Offset 0x06 - Mpc8240 PCI Status Register Bits */
#define MPC8240_PCI_PARITY_ERR 0x8000 /* PCI data or addr parity error */
#define MPC8240_PCI_SYS_ERR 0x4000 /* Mpc8240 asserts SERR */
#define MPC8240_PCI_RCV_MSTR_ABORT 0x2000 /* Mpc8240 issued PCI master abort */
#define MPC8240_PCI_RCV_TGT_ABORT 0x1000 /* received a PCI target abort */
#define MPC8240_PCI_SIG_TGT_ABORT 0x0800 /* Mpc8240 issued PCI target abort */
#define MPC8240_PCI_DATA_PARITY 0x0100 /* data parity error detected */
/* Offset 0x0D - Latency Timer register */
#define MPC8240_LAT_MAX_HOLD 0xf8 /* max PCI clocks for bus hold */
#define MPC8240_LAT_MIN_LAT 0x07 /* min latency timer value */
/* Offset 0x46 - PCI arbiter control Register */
#define MPC8240_PAC_IAE 0x00008000 /* internal arbiter enabled */
#define MPC8240_PAC_PARK_MASK 0x00006000 /* park mode control mask */
#define MPC8240_PAC_PARK_LAST 0x00000000 /* park mode cntrl, last device */
#define MPC8240_PAC_PARK_REQ0 0x00002000 /* park mode using REQ0/GNT0) */
#define MPC8240_PAC_PARK_MPC8240 0x00004000 /* park mode control (Mpc8240) */
#define MPC8240_PAC_RPCC 0x00000400 /* retry PCI configuration cycle */
#define MPC8240_PAC_PPRI_LVL 0x00000080 /* 8240 priority level: 1=high */
#define MPC8240_PAC_EDPL_MASK 0x0000000f /* ext dev priority lvl mask */
#define MPC8240_PAC_EDPL_REQ0 0x00000008 /* ext dev pty lvl REQ3/GNT3 */
#define MPC8240_PAC_EDPL_REQ1 0x00000004 /* ext dev pty lvl REQ2/GNT2 */
#define MPC8240_PAC_EDPL_REQ2 0x00000002 /* ext dev pty lvl REQ1/GNT1 */
#define MPC8240_PAC_EDPL_REQ3 0x00000001 /* ext dev pty lvl REQ0/GNT0 */
/* Offset 0x70 - power management configuration #1 Register */
#define MPC8240_PMC1_NO_NAP_MSG 0x00008000 /* no message before nap */
#define MPC8240_PMC1_NO_SLEEP_MSG 0x00004000 /* no message before sleep */
#define MPC8240_PMC1_LP_REF_EN 0x00001000 /* rfrsh enbl in low pwr mode */
#define MPC8240_PMC1_SUSP_QACK 0x00000400 /* QACK_ enable */
#define MPC8240_PMC1_PM 0x00000080 /* power mananagement enable */
#define MPC8240_PMC1_DOZE 0x00000020 /* doze mode */
#define MPC8240_PMC1_NAP 0x00000010 /* nap mode */
#define MPC8240_PMC1_SLEEP 0x00000008 /* sleep mode */
#define MPC8240_PMC1_CKO_MODE_MASK 0x00000006 /* clock output mode - mask */
#define MPC8240_PMC1_CKO_MODE_D 0x00000000 /* clk output mode - disable */
#define MPC8240_PMC1_CKO_MODE_S 0x00000002 /* clk out mode - system clk */
#define MPC8240_PMC1_CKO_MODE_1H 0x00000004 /* clk out mode - 1/2 PCI rate */
#define MPC8240_PMC1_CKO_MODE_P 0x00000006 /* clk out mode - PCI rate */
#define MPC8240_PMC1_CKO_SEL 0x00000001 /* clk out mode select */
/* Offset 0x72 - power management configuration #2 Register */
#define MPC8240_PMC2_DLL_EXTEND 0x00000080 /* extend DLL by a half clock */
#define MPC8240_PMC2_PCI_OHD_MASK 0x00000070 /* PCI out hold delay (mask) */
#define MPC8240_PMC2_PCI_OHD_SHIFT 4 /* PCI out hold delay (shift) */
#define MPC8240_PMC2_SLEEP 0x00000004 /* get PLL when exiting sleep */
#define MPC8240_PMC2_SUSPEND 0x00000002 /* get PLL when exiting suspend*/
#define MPC8240_PMC2_SHARED_MCP 0x00000001 /* disable MCP assertion */
/* Offset 0x73 - output driver control Register */
#define MPC8240_ODC_DRV_PCI 0x00000080 /* PCI drive: 0=hi, 1=med */
#define MPC8240_ODC_DRV_STD 0x00000040 /* STD drive: 0=hi, 1=med */
#define MPC8240_ODC_DRV_MEM_CTRL_MASK 0x00000030 /* mem ctrl drive: mask */
#define MPC8240_ODC_DRV_MEM_CTRL_40 0x00000000 /* mem ctrl drive: 40-ohms */
#define MPC8240_ODC_DRV_MEM_CTRL_20 0x00000010 /* mem ctrl drive: 20-ohms */
#define MPC8240_ODC_DRV_MEM_CTRL_13_3 0x00000020 /* mem ctrl drive: 13.3-ohms */
#define MPC8240_ODC_DRV_MEM_CTRL_8 0x00000030 /* mem ctrl drive: 8-ohms */
#define MPC8240_ODC_DRV_PCI_CLK_MASK 0x0000000c /* PCI clock drive: mask */
#define MPC8240_ODC_DRV_PCI_CLK_40 0x00000000 /* PCI clock drive: 40-ohms */
#define MPC8240_ODC_DRV_PCI_CLK_20 0x00000004 /* PCI clock drive: 20-ohms */
#define MPC8240_ODC_DRV_PCI_CLK_13_3 0x00000008 /* PCI clock drive: 13.3-ohms */
#define MPC8240_ODC_DRV_PCI_CLK_8 0x0000000c /* PCI clock drive: 8-ohms */
#define MPC8240_ODC_DRV_MEM_CLK_MASK 0x00000003 /* mem clock drive: mask */
#define MPC8240_ODC_DRV_MEM_CLK_40 0x00000000 /* mem clock drive: 40-ohms */
#define MPC8240_ODC_DRV_MEM_CLK_20 0x00000001 /* mem clock drive: 20-ohms */
#define MPC8240_ODC_DRV_MEM_CLK_13_3 0x00000002 /* mem clock drive: 13.3-ohms */
#define MPC8240_ODC_DRV_MEM_CLK_8 0x00000003 /* mem clock drive: 8-ohms */
/* Offset 0x74 - clock driver control Register */
#define MPC8240_CDC_PCI_CLK_0 0x00004000 /* PCI_CLK(0) disable */
#define MPC8240_CDC_PCI_CLK_1 0x00002000 /* PCI_CLK(1) disable */
#define MPC8240_CDC_PCI_CLK_2 0x00001000 /* PCI_CLK(2) disable */
#define MPC8240_CDC_PCI_CLK_3 0x00000800 /* PCI_CLK(3) disable */
#define MPC8240_CDC_PCI_CLK_4 0x00000400 /* PCI_CLK(4) disable */
#define MPC8240_CDC_SDRAM_CLK_0 0x00000040 /* SDRAM_CLK(0) disable */
#define MPC8240_CDC_SDRAM_CLK_1 0x00000020 /* SDRAM_CLK(1) disable */
#define MPC8240_CDC_SDRAM_CLK_2 0x00000010 /* SDRAM_CLK(2) disable */
#define MPC8240_CDC_SDRAM_CLK_3 0x00000008 /* SDRAM_CLK(3) disable */
/* Offset 0xA8 - processor interface configuration #1 Register */
#define MPC8240_PIC1_CF_BREAD_WS_MASK 0x00c00000 /* wait states mask */
#define MPC8240_PIC1_CF_BREAD_WS_SHIFT 22 /* wait states shift */
#define MPC8240_PIC1_RCS0 0x00100000 /* ROM location */
#define MPC8240_PIC1_PROC_TYPE_MASK 0x00060000 /* processor type mask */
#define MPC8240_PIC1_PROC_TYPE_SHIFT 17 /* processor type shift */
#define MPC8240_PIC1_ADDRESS_MAP 0x00010000 /* address map */
#define MPC8240_PIC1_FLASH_WR_EN 0x00001000 /* FLASH write enable */
#define MPC8240_PIC1_MCP_EN 0x00000800 /* machine check enable */
#define MPC8240_PIC1_CF_DPARK 0x00000200 /* processor data bus park */
#define MPC8240_PIC1_STORE_GATHER 0x00000040 /* store gathering enable */
#define MPC8240_PIC1_ENDIAN_MODE 0x00000020 /* endian mode */
#define MPC8240_PIC1_CF_LOOP_SNOOP 0x00000010 /* PCI-to-mem snoop loop en */
#define MPC8240_PIC1_CF_APARK 0x00000008 /* processor addr bus park */
#define MPC8240_PIC1_SPECULATIVE 0x00000004 /* speculative PCI from */
/* memory read enable */
/* Offset 0xAC - processor interface configuration #2 Register */
#define MPC8240_PIC2_NO_SER_ON_CFG 0x20000000 /* disable PCI serialization */
#define MPC8240_PIC2_NO_SNOOP_EN 0x08000000 /* disable PCI snoop */
#define MPC8240_PIC2_CF_FF0_LOCAL 0x04000000 /* ROM PCI address map */
/* #define MPC8240_PIC2_CF_FF0_LOCAL 0x08000000 */ /* modify by zoutl for test 2003-4-29 17:39 */
#define MPC8240_PIC2_FLSH_WR_LCK_EN 0x02000000 /* disable FLASH writes */
#define MPC8240_PIC2_CF_SNOOP_WS_M 0x00c00000 /* snoop addr phase wait state*/
#define MPC8240_PIC2_CF_SNOOP_WS_S 18 /* snoop addr wait shift */
#define MPC8240_PIC2_CF_APHASE_WS_M 0x0000000c /* proc addr phase wait states*/
#define MPC8240_PIC2_CF_APHASE_WS_S 2 /* proc addr phase wait shift */
/* Offset 0xE0 - emulation support */
#define MPC8240_ES_CPU_FD_ALIAS_EN 0x00000080 /* forward FDxxxxxx to PCI */
#define MPC8240_ES_PCI_FD_ALIAS_EN 0x00000040 /* forward FDxxxxxx to CPU */
#define MPC8240_ES_DLL_RESET 0x00000020 /* reset the DLL */
#define MPC8240_ES_PCI_COMPAT_HOLE 0x00000008 /* PCI compatibil hole enable */
#define MPC8240_ES_PROC_COMPAT_HOLE 0x00000004 /* proc compatibility hole en */
/* Offset 0xC0 - error enable #1 Register */
#define MPC8240_EE1_PCI_TARG_ABORT 0x00000080 /* PCI target abort */
#define MPC8240_EE1_PCI_PERR_SLAVE 0x00000040 /* PCI slace PERR */
#define MPC8240_EE1_MEM_SELECT 0x00000020 /* memory select */
#define MPC8240_EE1_MEM_REFRESH 0x00000010 /* memory refresh overflow */
#define MPC8240_EE1_PCI_PERR_MSTR 0x00000008 /* PCI master PERR */
#define MPC8240_EE1_MEM_READ_PARITY 0x00000004 /* memory read parity */
#define MPC8240_EE1_PCI_MSTR_ABORT 0x00000002 /* PCI master abort */
#define MPC8240_EE1_LOCAL_BUS_ERROR 0x00000001 /* local bus error */
/* Offset 0xC1 - error detection #1 Register */
#define MPC8240_ED1_SERR 0x00000080 /* SERR_ received */
#define MPC8240_ED1_PCI_PERR_SLAVE 0x00000040 /* PCI slace PERR */
#define MPC8240_ED1_MEM_SELECT 0x00000020 /* memory select */
#define MPC8240_ED1_MEM_REFRESH 0x00000010 /* memory refresh overflow */
#define MPC8240_ED1_CYCLE_SPACE 0x00000008 /* cycle type: 0=local, 1=PCI */
#define MPC8240_ED1_MEM_READ_PARITY 0x00000004 /* memory read parity */
#define MPC8240_ED1_ULBC_MASK 0x00000003 /* unsupported local bus */
/* cycle mask */
#define MPC8240_ED1_ULBC_NO_ERROR 0x00000000 /* no error detected */
#define MPC8240_ED1_ULBC_UTA 0x00000001 /* unsupported transfer */
/* attributes */
/* Offset 0xC3 - CPU Bus Error Status Register */
#define MPC8240_CPU_BUS_ERR_TT_MASK 0x000000f8
#define MPC8240_CPU_BUS_ERR_TSIZ_MASK 0x00000007
/* Offset 0xC4 - error enable #2 */
#define MPC8240_EE2_PCI_ADRS_PARITY 0x00000080 /* PCI address parity error */
#define MPC8240_EE2_ECC_MULTIBIT 0x00000008 /* ECC multi-bit error */
#define MPC8240_EE2_60X_MEM_WRITE_P 0x00000004 /* 60X mem write parity error */
#define MPC8240_EE2_FLASH_ROM_WRITE 0x00000001 /* Flash ROM write error */
/* Offset 0xC5 - error detection #2 Register */
#define MPC8240_ED2_IEA 0x00000080 /* invalid error address */
#define MPC8240_ED2_ECC_MULTIBIT 0x00000008 /* ECC multi-bit error */
#define MPC8240_ED2_60X_MEM_WRITE_P 0x00000004 /* 60X mem write parity error */
#define MPC8240_ED2_FLASH_ROM_WRITE 0x00000001 /* Flash ROM write error */
/* Offset 0xC7 - PCI Bus Error Status Register */
#define MPC8240_CPU_BUS_TARGET 0x00000010 /* 1=bus target, 0=bus master */
#define MPC8240_CPU_BUS_ERR_C_BE_MASK 0x0000000f /* Bus Error Status mask */
/* Offset 0xF0 - memory control configuration #1 */
#define MPC8240_MCC1_ROMNAL_MASK 0xf0000000 /* ROM nibble access time mask*/
#define MPC8240_MCC1_ROMNAL_SHIFT 28 /* ROM nibble access time shft*/
#define MPC8240_MCC1_ROMFAL_MASK 0x0f800000 /* ROM first access time mask */
#define MPC8240_MCC1_ROMFAL_SHIFT 23 /* ROM first access time shift*/
#define MPC8240_MCC1_DBUS_SIZE_MASK 0x00600000 /* ROM/FLASH DBUS size mask */
#define MPC8240_MCC1_64N32 0x00400000 /* 64-bit external data path */
#define MPC8240_MCC1_8N64 0x00200000 /* 8-bit ROM/Flash */
#define MPC8240_MCC1_BURST 0x00100000 /* burst mode ROM */
#define MPC8240_MCC1_MEMGO 0x00080000 /* enable RAM interface logic */
#define MPC8240_MCC1_SREN 0x00040000 /* enable self refresh */
#define MPC8240_MCC1_RAM_TYPE 0x00020000 /* RAM type: 0=SDRAM,1=FPM/EDO*/
#define MPC8240_MCC1_PCKEN 0x00010000 /* enable parity checking */
#define MPC8240_MCC1_ROW_ADRS_MASK 0x0000ffff /* row address mask */
/* Offset 0xF4 - memory control configuration #2 Register */
#define MPC8240_MCC2_TS_WAIT_TIMER_M 0xe0000000 /* ROM out disable timing */
#define MPC8240_MCC2_TS_WAIT_TIMER_S 29 /* mask and shift */
#define MPC8240_MCC2_ASRISE_MASK 0x1e000000 /* AS_ falling edge timing */
#define MPC8240_MCC2_ASRISE_SHIFT 25 /* mask and shift */
#define MPC8240_MCC2_ASFALL_MASK 0x01e00000 /* AS_ rising edge timing */
#define MPC8240_MCC2_ASFALL_SHIFT 21 /* mask and shift */
#define MPC8240_MCC2_PARITY_OR_ECC 0x00100000 /* ECC/parity mechanism */
#define MPC8240_MCC2_WR_PAR_CHK_EN 0x00080000 /* write parity check enable */
#define MPC8240_MCC2_RD_PARECC_EN 0x00040000 /* inline mem bus read parity*/
#define MPC8240_MCC2_ECCEN 0x00020000 /* ECC enable */
#define MPC8240_MCC2_EDO 0x00010000 /* EDO DRAM */
#define MPC8240_MCC2_REFINT_MASK 0x0000fffc /* refresh interval mask */
#define MPC8240_MCC2_REFINT_SHIFT 2 /* refresh interval shift */
#define MPC8240_MCC2_RSV_PG 0x00000002 /* reserve 1 page */
#define MPC8240_MCC2_RMW_PAR 0x00000001 /* parity gather/store */
/* Offset 0xF8 - memory control configuration #3 Register */
#define MPC8240_MCC3_BSTOPRE_25_M 0xf0000000 /* burst to precharge timing */
#define MPC8240_MCC3_BSTOPRE_25_S 28 /* mask and shift */
#define MPC8240_MCC3_REFREC_MASK 0x0f000000 /* refresh to active interval*/
#define MPC8240_MCC3_REFREC_SHIFT 24 /* timing mask and shift */
#define MPC8240_MCC3_RDLAT_MASK 0x00f00000 /* read data latency timing */
#define MPC8240_MCC3_RDLAT_SHIFT 20 /* mask and shift */
#define MPC8240_MCC3_CPX 0x00080000 /* CAS write timing */
#define MPC8240_MCC3_RAS6P_MASK 0x00078000 /* RAS low time for CBR */
#define MPC8240_MCC3_RAS6P_SHIFT 15 /* refresh shift and mask */
#define MPC8240_MCC3_CAS5_MASK 0x00007000 /* CAS low time for page mode*/
#define MPC8240_MCC3_CAS5_SHIFT 12 /* access mask and shift */
#define MPC8240_MCC3_CP4_MASK 0x00000e00 /* CAS precharge mask */
#define MPC8240_MCC3_CP4_SHIFT 9 /* CAS precharge shift */
#define MPC8240_MCC3_CAS3_MASK 0x000001c0 /* CAS low time for first */
#define MPC8240_MCC3_CAS3_SHIFT 6 /* data access mask and shift*/
#define MPC8240_MCC3_RCD2_MASK 0x00000038 /* RAS to CAS delay mask */
#define MPC8240_MCC3_RCD2_SHIFT 3 /* RAS to CAS delay shift */
#define MPC8240_MCC3_RP1_MASK 0x00000007 /* RAS precharge mask */
/* Offset 0xFC - memory control configuration #4 Register */
#define MPC8240_MCC4_PRETOACT_MASK 0xf0000000 /* precharge to active */
#define MPC8240_MCC4_PRETOACT_SHIFT 28 /* interval mask and shift */
#define MPC8240_MCC4_ACTOPRE_MASK 0x0f000000 /* active to precharge */
#define MPC8240_MCC4_ACTOPRE_SHIFT 24 /* interval mask and shift */
#define MPC8240_MCC4_INLINE 0x00400000 /* inline ECC/parity chk enbl*/
#define MPC8240_MCC4_REGISTERED 0x00100000 /* memory data interface */
#define MPC8240_MCC4_BSTOPRE_01_MASK 0x000c0000 /* burst to precharge timing */
#define MPC8240_MCC4_BSTOPRE_01_SHIFT 18 /* mask and shift */
#define MPC8240_MCC4_REGDIMM 0x00008000 /* config mem bus for DIMMs */
#define MPC8240_MCC4_SDMODE_CAS_SHF 12 /* CAS latency type shift */
#define MPC8240_MCC4_SDMODE_MASK 0x00007f00 /* SDRAM mode mask */
#define MPC8240_MCC4_SDMODE_SHIFT 8 /* SDRAM mode shift */
#define MPC8240_MCC4_ACTORW_MASK 0x000000f0 /* activate to read/write */
#define MPC8240_MCC4_ACTORW_SHIFT 4 /* interval mask and shift */
#define MPC8240_MCC4_BSTOPRE_69_MASK 0x0000000f /* burst to prechrg timing msk*/
/* I2C register bit definitions */
/* I2C control register */
#define MPC8240_I2C_C_MEN 0x00000080 /* module enable */
#define MPC8240_I2C_C_MIEN 0x00000040 /* module interrupt enable */
#define MPC8240_I2C_C_MSTA 0x00000020 /* master/salve mode select */
#define MPC8240_I2C_C_MTX 0x00000010 /* xmit/recv mode select */
#define MPC8240_I2C_C_TXAK 0x00000008 /* transfer acknowledge enabl */
#define MPC8240_I2C_C_RSTA 0x00000004 /* repeat start */
/* I2C status register */
#define MPC8240_I2C_S_MCF 0x00000080 /* data transfer */
#define MPC8240_I2C_S_MAAS 0x00000040 /* addressed as a slave */
#define MPC8240_I2C_S_MBB 0x00000020 /* bus busy */
#define MPC8240_I2C_S_MAL 0x00000010 /* arbitration lost */
#define MPC8240_I2C_S_SRW 0x00000004 /* slave read/write */
#define MPC8240_I2C_S_MIF 0x00000002 /* interrupt */
#define MPC8240_I2C_S_RXAK 0x00000001 /* received acknowledge */
/* EPIC register bit definitions */
/* EPIC Feature Reporting register */
#define EPIC_NIRQ 0x07ff0000 /* number of IRQs */
#define EPIC_NCPU 0x00001f00 /* number of CPUs supported */
#define EPIC_VID 0x000000ff /* version ID */
/* EPIC global configuration register */
#define EPIC_GC_RESET 0x80000000 /* reset controller */
#define EPIC_GC_MIXED 0x20000000 /* mixed mode interrupts */
/* EPIC interrupt configuration register */
#define EPIC_IC_R_MASK 0x70000000 /* clock ratio mask */
#define EPIC_IC_R_SHFT 28 /* clock ratio shift value */
#define EPIC_IC_R_VALUE 4 /* clock ratio value */
#define EPIC_IC_SIE 0x08000000 /* serial interrupt enable */
/* EPIC Vendor Identification */
#define EPIC_STEP 0x00ff0000 /* device silicon revision no. */
/* EPIC processor initialization register */
#define EPIC_PI_P0 0x00000001 /* soft reset to processor 0 */
/* EPIC global timer count register */
#define EPIC_GTC_T 0x80000000 /* toggle */
#define EPIC_GTC_C_MASK 0x7FFFFFFF /* count mask */
/* EPIC global timer base count register */
#define EPIC_GTBC_CI 0x80000000 /* count inhibit */
#define EPIC_GTBC_C_MASK 0x7FFFFFFF /* base count mask */
/* EPIC global timer vector/priority register */
#define EPIC_GTVP_M 0x80000000 /* mask interrupt */
#define EPIC_GTVP_A 0x40000000 /* interrupt requested/in-srvce */
#define EPIC_GTVP_PRI_MASK 0x000f0000 /* global timer priority mask */
#define EPIC_GTVP_PRI_0 0x00000000 /* priority 0 (disabled) */
#define EPIC_GTVP_PRI_1 0x00010000 /* priority 1 */
#define EPIC_GTVP_PRI_2 0x00020000 /* priority 2 */
#define EPIC_GTVP_PRI_3 0x00030000 /* priority 3 */
#define EPIC_GTVP_PRI_4 0x00040000 /* priority 4 */
#define EPIC_GTVP_PRI_5 0x00050000 /* priority 5 */
#define EPIC_GTVP_PRI_6 0x00060000 /* priority 6 */
#define EPIC_GTVP_PRI_7 0x00070000 /* priority 7 */
#define EPIC_GTVP_PRI_8 0x00080000 /* priority 8 */
#define EPIC_GTVP_PRI_9 0x00090000 /* priority 9 */
#define EPIC_GTVP_PRI_10 0x000a0000 /* priority 10 */
#define EPIC_GTVP_PRI_11 0x000b0000 /* priority 11 */
#define EPIC_GTVP_PRI_12 0x000c0000 /* priority 12 */
#define EPIC_GTVP_PRI_13 0x000d0000 /* priority 13 */
#define EPIC_GTVP_PRI_14 0x000e0000 /* priority 14 */
#define EPIC_GTVP_PRI_15 0x000f0000 /* priority 15 */
#define EPIC_GTVP_V_MASK 0x000000ff /* vector mask */
/* EPIC global timer destination register */
#define EPIC_GTD_P0 0x00000001 /* direct to processor 0 */
/* EPIC external/serial/dma source vector/priority registers */
#define EPIC_SRC_MASK 0x80000000 /* mask interrupt */
#define EPIC_SRC_ACT 0x40000000 /* intr requested/in-service */
#define EPIC_SRC_PLR 0x00800000 /* polarity (0/1=lo-neg/hi-pos) */
#define EPIC_SRC_SENS 0x00400000 /* sense (0/1=edge/level) */
#define EPIC_SRC_PRI_MASK 0x000f0000 /* source priority mask */
#define EPIC_SRC_PRI_0 0x00000000 /* priority 0 (disabled) */
#define EPIC_SRC_PRI_1 0x00010000 /* priority 1 */
#define EPIC_SRC_PRI_2 0x00020000 /* priority 2 */
#define EPIC_SRC_PRI_3 0x00030000 /* priority 3 */
#define EPIC_SRC_PRI_4 0x00040000 /* priority 4 */
#define EPIC_SRC_PRI_5 0x00050000 /* priority 5 */
#define EPIC_SRC_PRI_6 0x00060000 /* priority 6 */
#define EPIC_SRC_PRI_7 0x00070000 /* priority 7 */
#define EPIC_SRC_PRI_8 0x00080000 /* priority 8 */
#define EPIC_SRC_PRI_9 0x00090000 /* priority 9 */
#define EPIC_SRC_PRI_10 0x000a0000 /* priority 10 */
#define EPIC_SRC_PRI_11 0x000b0000 /* priority 11 */
#define EPIC_SRC_PRI_12 0x000c0000 /* priority 12 */
#define EPIC_SRC_PRI_13 0x000d0000 /* priority 13 */
#define EPIC_SRC_PRI_14 0x000e0000 /* priority 14 */
#define EPIC_SRC_PRI_15 0x000f0000 /* priority 15 */
#define EPIC_SRC_VEC_MASK 0x000000ff /* vector mask */
#define EPIC_SRC_POLARITY_HIGH EPIC_SRC_PLR
#define EPIC_SRC_POLARITY_LOW 0
#define EPIC_SRC_SENSE_LEVEL EPIC_SRC_SENS
#define EPIC_SRC_SENSE_EDGE 0
/* EPIC external source destination register */
#define EPIC_ESD_P0 0x00000001 /* direct to processor 0 */
/* EPIC processor current task priority register */
#define EPIC_TASK_PRI_MASK 0x0000000f /* task priority mask bits */
#define EPIC_TASK_PRI_0 0x00000000 /* priority 0 */
#define EPIC_TASK_PRI_1 0x00000001 /* priority 1 */
#define EPIC_TASK_PRI_2 0x00000002 /* priority 2 */
#define EPIC_TASK_PRI_3 0x00000003 /* priority 3 */
#define EPIC_TASK_PRI_4 0x00000004 /* priority 4 */
#define EPIC_TASK_PRI_5 0x00000005 /* priority 5 */
#define EPIC_TASK_PRI_6 0x00000006 /* priority 6 */
#define EPIC_TASK_PRI_7 0x00000007 /* priority 7 */
#define EPIC_TASK_PRI_8 0x00000008 /* priority 8 */
#define EPIC_TASK_PRI_9 0x00000009 /* priority 9 */
#define EPIC_TASK_PRI_10 0x0000000a /* priority 10 */
#define EPIC_TASK_PRI_11 0x0000000b /* priority 11 */
#define EPIC_TASK_PRI_12 0x0000000c /* priority 12 */
#define EPIC_TASK_PRI_13 0x0000000d /* priority 13 */
#define EPIC_TASK_PRI_14 0x0000000e /* priority 14 */
#define EPIC_TASK_PRI_15 0x0000000f /* priority 15 (masked) */
/* Message Unit (I2O) Register Bit Definitions */
/* Outbound Message Interrupt Status Register */
#define MPC8240_I2O_OPQI 0x00000020 /* Outbound Post Queue Intr */
#define MPC8240_I2O_ODI 0x00000008 /* Outbound Doorbell Intr */
#define MPC8240_I2O_OM1I 0x00000002 /* Outbound Message 1 Intr */
#define MPC8240_I2O_OM0I 0x00000001 /* Outbound Message 0 Intr */
/* Outbound Message Interrupt Mask Register */
#define MPC8240_I2O_OPQIM 0x00000020 /* Out Post Queue Intr Mask */
#define MPC8240_I2O_ODIM 0x00000008 /* Out Doorbell Intr Mask */
#define MPC8240_I2O_OM1IM 0x00000002 /* Outbound Msg 1 Intr Mask */
#define MPC8240_I2O_OM0IM 0x00000001 /* Outbound Msg 0 Intr Mask */
/* Inbound Message Interrupt Status Register */
#define MPC8240_I2O_OFOI 0x00000100 /* Outbound Free Ovrflw Intr */
#define MPC8240_I2O_IPOI 0x00000080 /* Inbound Post Overflow Intr */
#define MPC8240_I2O_IPQI 0x00000020 /* Inbound Post Queue Intr */
#define MPC8240_I2O_MCI 0x00000010 /* Machine Check Intr */
#define MPC8240_I2O_IDI 0x00000008 /* Inbound Doorbell Intr */
#define MPC8240_I2O_IM1I 0x00000002 /* Inbound Message 1 Intr */
#define MPC8240_I2O_IM0I 0x00000001 /* Inbound Message 0 Intr */
/* Inbound Message Interrupt Mask Register */
#define MPC8240_I2O_OFOIM 0x00000100 /* Outbound Free Ovrflw Mask */
#define MPC8240_I2O_IPOIM 0x00000080 /* Inbound Post Overflow Mask */
#define MPC8240_I2O_IPQIM 0x00000020 /* Inbound Post Queue Mask */
#define MPC8240_I2O_MCIM 0x00000010 /* Machine Check Mask */
#define MPC8240_I2O_IDIM 0x00000008 /* Inbound Doorbell Mask */
#define MPC8240_I2O_IM1IM 0x00000002 /* Inbound Message 1 Mask */
#define MPC8240_I2O_IM0IM 0x00000001 /* Inbound Message 0 Mask */
/* Inbound FIFO Pointer Registers */
#define MPC8240_I2O_IN_QBA 0xfff00000 /* Inbound Queue Base Addr */
#define MPC8240_I2O_IN_FIFO_PTR 0x000ffffc /* In FIFO pointer offset */
/* Outbound FIFO Pointer Registers */
#define MPC8240_I2O_OUT_QBA 0xfff00000 /* Outbound Queue Base Addr */
#define MPC8240_I2O_OUT_FIFO_PTR 0x000ffffc /* Out FIFO pointer offset */
/* I2O Messaging Unit Control Register */
#define MPC8240_I2O_CQS 0x0000003e /* circular queue size mask */
#define MPC8240_I2O_CQS_16K 0x00000002 /* 4K entries, 16K bytes */
#define MPC8240_I2O_CQS_32K 0x00000004 /* 8K entries, 32K bytes */
#define MPC8240_I2O_CQS_64K 0x00000008 /* 16K entries, 64K bytes */
#define MPC8240_I2O_CQS_128K 0x00000010 /* 32K entries, 128K bytes */
#define MPC8240_I2O_CQS_256K 0x00000020 /* 64K entries, 256K bytes */
#define MPC8240_I2O_CQE 0x00000001 /* circular queue enable */
/* I2O Queue Base Address Register */
#define MPC8240_I2O_QBA 0xfff00000 /* queue base address bits */
#ifdef __cplusplus
}
#endif
#endif /* INCmpc8240h */