www.pudn.com > f2812_uart.rar > F281X.H
/* =============================================================================
filename: F2812.h
Description: TMS320F281X register definitions for c
=============================================================================== */
#ifndef _F2812_h
#define _F2812_h
/*====================== PLL, Clocking, Watchdog, and Low-Power Mode Registers =====================*/
/* reserved 0x00 7010 ~ 0x00 7017 8 */
/* reserved 0x00 7018 1 */
/* reserved 0x00 7019 1 */
#define HISPCP *((volatile unsigned int *)0x00701A) /* 1 High-Speed Peripheral Clock Prescaler Register for HSPCLK clock */
#define LOSPCP *((volatile unsigned int *)0x00701B) /* 1 Low-Speed Peripheral Clock Prescaler Register for LSPCLK clock */
#define PCLKCR *((volatile unsigned int *)0x00701C) /* 1 Peripheral Clock Control Register */
/* reserved 0x00 701D 1 */
#define LPMCR0 *((volatile unsigned int *)0x00701E) /* 1 Low Power Mode Control Register 0 */
#define LPMCR1 *((volatile unsigned int *)0x00701F) /* 1 Low Power Mode Control Register 1 */
/* reserved 0x00 7020 1 */
#define PLLCR *((volatile unsigned int *)0x007021) /* 1 PLL Control Register */
#define SCSR *((volatile unsigned int *)0x007022) /* 1 System Control & Status Register */
#define WDCNTR *((volatile unsigned int *)0x007023) /* 1 Watchdog Counter Register */
/* reserved 0x00 7024 1 */
#define WDKEY *((volatile unsigned int *)0x007025) /* 1 Watchdog Reset Key Register */
/* reserved 0x00 7026 ~ 0x00 7028 3 */
#define WDCR *((volatile unsigned int *)0x007029) /* 1 Watchdog Control Register */
/* reserved 0x00 702A ~ 0x00 702F 6 */
/*================= Flash/OTP Configuration Registers =======================*/
#define FOPT *((volatile unsigned int *)0x00000A80) /* Flash Option Register */
/* 0x00000A81 Reserved */
#define FPWR *((volatile unsigned int *)0x00000A82) /* Flash Power Modes Register */
#define FSTATUS *((volatile unsigned int *)0x00000A83) /* Status Register */
#define FSTDBYWAIT *((volatile unsigned int *)0x00000A84) /* Flash Sleep To Standby Wait State Register */
#define FACTIVEWAIT *((volatile unsigned int *)0x00000A85) /* Flash Standby To Active Wait State Register */
#define FBANKWAIT *((volatile unsigned int *)0x00000A86) /* Flash Read Access Wait State Register */
#define FOTPWAIT *((volatile unsigned int *)0x00000A87) /* OTP Read Access Wait State Register */
/*============= Code Security Module (CSM) Registers ================================*/
/* KEY Registers ¨C Accessible by the user */
#define KEY0 *((volatile unsigned int *)0x00000AE0) /* Low word of the 128-bit KEY register,Reset Values: 0xFFFF */
#define KEY1 *((volatile unsigned int *)0x00000AE1) /* word of the 128-bit KEY register,Reset Values: 0xFFFF */
#define KEY2 *((volatile unsigned int *)0x00000AE2) /* word of the 128-bit KEY register,Reset Values: 0xFFFF */
#define KEY3 *((volatile unsigned int *)0x00000AE3) /* word of the 128-bit KEY register,Reset Values: 0xFFFF */
#define KEY4 *((volatile unsigned int *)0x00000AE4) /* word of the 128-bit KEY register,Reset Values: 0xFFFF */
#define KEY5 *((volatile unsigned int *)0x00000AE5) /* word of the 128-bit KEY register,Reset Values: 0xFFFF */
#define KEY6 *((volatile unsigned int *)0x00000AE6) /* word of the 128-bit KEY register,Reset Values: 0xFFFF */
#define KEY7 *((volatile unsigned int *)0x00000AE7) /* High word of the 128-bit KEY register,Reset Values: 0xFFFF */
#define CSMSCR *((volatile unsigned int *)0x00000AEF) /* CSM status and control register */
/*========= PIE Configurations and Control Register Mappings ================*/
#define PIECTRL *((volatile unsigned int *)0x000CE0) /* Control Register */
#define PIEACK *((volatile unsigned int *)0x000CE1) /* Acknowledge Register */
#define PIEIER1 *((volatile unsigned int *)0x000CE2) /* 1 PIE, INT1 Group Enable Register */
#define PIEIFR1 *((volatile unsigned int *)0x000CE3) /* 1 PIE, INT1 Group Flag Register */
#define PIEIER2 *((volatile unsigned int *)0x000CE4) /* 1 PIE, INT2 Group Enable Register */
#define PIEIFR2 *((volatile unsigned int *)0x000CE5) /* 1 PIE, INT2 Group Flag Register */
#define PIEIER3 *((volatile unsigned int *)0x000CE6) /* 1 PIE, INT3 Group Enable Register */
#define PIEIFR3 *((volatile unsigned int *)0x000CE7) /* 1 PIE, INT3 Group Flag Register */
#define PIEIER4 *((volatile unsigned int *)0x000CE8) /* 1 PIE, INT4 Group Enable Register */
#define PIEIFR4 *((volatile unsigned int *)0x000CE9) /* 1 PIE, INT4 Group Flag Register */
#define PIEIER5 *((volatile unsigned int *)0x000CEA) /* 1 PIE, INT5 Group Enable Register */
#define PIEIFR5 *((volatile unsigned int *)0x000CEB) /* 1 PIE, INT5 Group Flag Register */
#define PIEIER6 *((volatile unsigned int *)0x000CEC) /* 1 PIE, INT6 Group Enable Register */
#define PIEIFR6 *((volatile unsigned int *)0x000CED) /* 1 PIE, INT6 Group Flag Register */
#define PIEIER7 *((volatile unsigned int *)0x000CEE) /* 1 PIE, INT7 Group Enable Register */
#define PIEIFR7 *((volatile unsigned int *)0x000CEF) /* 1 PIE, INT7 Group Flag Register */
#define PIEIER8 *((volatile unsigned int *)0x000CF0) /* 1 PIE, INT8 Group Enable Register */
#define PIEIFR8 *((volatile unsigned int *)0x000CF1) /* 1 PIE, INT8 Group Flag Register */
#define PIEIER9 *((volatile unsigned int *)0x000CF2) /* 1 PIE, INT9 Group Enable Register */
#define PIEIFR9 *((volatile unsigned int *)0x000CF3) /* 1 PIE, INT9 Group Flag Register */
#define PIEIER10 *((volatile unsigned int *)0x000CF4) /* 1 PIE, INT10 Group Enable Register */
#define PIEIFR10 *((volatile unsigned int *)0x000CF5) /* 1 PIE, INT10 Group Flag Register */
#define PIEIER11 *((volatile unsigned int *)0x000CF6) /* 1 PIE, INT11 Group Enable Register */
#define PIEIFR11 *((volatile unsigned int *)0x000CF7) /* 1 PIE, INT11 Group Flag Register */
#define PIEIER12 *((volatile unsigned int *)0x000CF8) /* 1 PIE, INT12 Group Enable Register */
#define PIEIFR12 *((volatile unsigned int *)0x000CF9) /* 1 PIE, INT12 Group Flag Register */
/* 0x000CFA ~ 0x000CFF 6 Words reserved */
/*========================= PIE Interrupt Vector ==========================================*/
/* 0x000D00 ~ 0x000d18 reserved , no used */
typedef interrupt void(*PINT)(void);
#define Reserved1_ISR *((volatile unsigned long *)0x000D00) /* reserved */
#define Reserved2_ISR *((volatile unsigned long *)0x000D02) /* reserved */
#define Reserved3_ISR *((volatile unsigned long *)0x000D04) /* reserved */
#define Reserved4_ISR *((volatile unsigned long *)0x000D06) /* reserved */
#define Reserved5_ISR *((volatile unsigned long *)0x000D08) /* reserved */
#define Reserved6_ISR *((volatile unsigned long *)0x000D0A) /* reserved */
#define Reserved7_ISR *((volatile unsigned long *)0x000D0C) /* reserved */
#define Reserved8_ISR *((volatile unsigned long *)0x000D0E) /* reserved */
#define Reserved9_ISR *((volatile unsigned long *)0x000D10) /* reserved */
#define Reserved10_ISR *((volatile unsigned long *)0x000D12) /* reserved */
#define Reserved11_ISR *((volatile unsigned long *)0x000D14) /* reserved */
#define Reserved12_ISR *((volatile unsigned long *)0x000D16) /* reserved */
#define Reserved13_ISR *((volatile unsigned long *)0x000D18) /* reserved */
#define INT13_ISR *((volatile unsigned long *)0x000D1A) /* XINT13 or CPU-Timer 1 */
#define INT14_ISR *((volatile unsigned long *)0x000D1C) /* CPU-Timer2 */
#define DATALOG_ISR *((volatile unsigned long *)0x000D1E) /* Datalogging interrupt */
#define RTOSINT_ISR *((volatile unsigned long *)0x000D20) /* RTOS interrupt */
#define EMUINT_ISR *((volatile unsigned long *)0x000D22) /* Emulation interrupt */
#define NMI_ISR *((volatile unsigned long *)0x000D24) /* Non-maskable interrupt */
#define ILLEGAL_ISR *((volatile unsigned long *)0x000D26) /* Illegal operation TRAP */
#define USER0_ISR *((volatile unsigned long *)0x000D28) /* User Defined trap 1 */
#define USER1_ISR *((volatile unsigned long *)0x000D2A) /* User Defined trap 1 */
#define USER2_ISR *((volatile unsigned long *)0x000D2C) /* User Defined trap 1 */
#define USER3_ISR *((volatile unsigned long *)0x000D2E) /* User Defined trap 1 */
#define USER4_ISR *((volatile unsigned long *)0x000D30) /* User Defined trap 1 */
#define USER5_ISR *((volatile unsigned long *)0x000D32) /* User Defined trap 1 */
#define USER6_ISR *((volatile unsigned long *)0x000D34) /* User Defined trap 1 */
#define USER7_ISR *((volatile unsigned long *)0x000D36) /* User Defined trap 1 */
#define USER8_ISR *((volatile unsigned long *)0x000D38) /* User Defined trap 1 */
#define USER9_ISR *((volatile unsigned long *)0x000D3A) /* User Defined trap 1 */
#define USER10_ISR *((volatile unsigned long *)0x000D3C) /* User Defined trap 1 */
#define USER11_ISR *((volatile unsigned long *)0x000D3E) /* User Defined trap 1 */
/*---------- Group 1 PIE Interrupt Service Routines -------------*/
#define PDPINTA_ISR *((volatile unsigned long *)0x000D40) /* EV-A */
#define PDPINTB_ISR *((volatile unsigned long *)0x000D42) /* EV-B */
#define REVD1_3 *((volatile unsigned long *)0x000D44) /* reserved */
#define XINT1_ISR *((volatile unsigned long *)0x000D46)
#define XINT2_ISR *((volatile unsigned long *)0x000D48)
#define ADCINT_ISR *((volatile unsigned long *)0x000D4A) /* ADC */
#define TINT0_ISR *((volatile unsigned long *)0x000D4C) /* CPUTimer 0 */
#define WAKEINT_ISR *((volatile unsigned long *)0x000D4E) /* WD */
/*----------- Group 2 PIE Interrupt Service Routines --------------*/
#define CMP1INT_ISR *((volatile unsigned long *)0x000D50) /* EV-A */
#define CMP2INT_ISR *((volatile unsigned long *)0x000D52) /* EV-A */
#define CMP3INT_ISR *((volatile unsigned long *)0x000D54) /* EV-A */
#define T1PINT_ISR *((volatile unsigned long *)0x000D56) /* EV-A */
#define T1CINT_ISR *((volatile unsigned long *)0x000D58) /* EV-A */
#define T1UFINT_ISR *((volatile unsigned long *)0x000D5A) /* EV-A */
#define T1OFINT_ISR *((volatile unsigned long *)0x000D5C) /* EV-A */
#define REVD2_8 *((volatile unsigned long *)0x000D5E) /* reserved */
/*--------- Group 3 PIE Interrupt Service Routines -------------------*/
#define T2PINT_ISR *((volatile unsigned long *)0x000D60) /* EV-A */
#define T2CINT_ISR *((volatile unsigned long *)0x000D62) /* EV-A */
#define T2UFINT_ISR *((volatile unsigned long *)0x000D64) /* EV-A */
#define T2OFINT_ISR *((volatile unsigned long *)0x000D66) /* EV-A */
#define CAPINT1_ISR *((volatile unsigned long *)0x000D68) /* EV-A */
#define CAPINT2_ISR *((volatile unsigned long *)0x000D6A) /* EV-A */
#define CAPINT3_ISR *((volatile unsigned long *)0x000D6C) /* EV-A */
#define REVD3_8 *((volatile unsigned long *)0x000D6E) /* reserved */
/*----------- Group 4 PIE Interrupt Service Routines --------------*/
#define CMP4INT_ISR *((volatile unsigned long *)0x000D70) /* EV-A */
#define CMP5INT_ISR *((volatile unsigned long *)0x000D72) /* EV-A */
#define CMP6INT_ISR *((volatile unsigned long *)0x000D74) /* EV-A */
#define T3PINT_ISR *((volatile unsigned long *)0x000D76) /* EV-A */
#define T3CINT_ISR *((volatile unsigned long *)0x000D78) /* EV-A */
#define T3UFINT_ISR *((volatile unsigned long *)0x000D7A) /* EV-A */
#define T3OFINT_ISR *((volatile unsigned long *)0x000D7C) /* EV-A */
#define REVD4_8 *((volatile unsigned long *)0x000D7E) /* reserved */
/*--------- Group 5 PIE Interrupt Service Routines -------------------*/
#define T4PINT_ISR *((volatile unsigned long *)0x000D80) /* EV-A */
#define T4CINT_ISR *((volatile unsigned long *)0x000D82) /* EV-A */
#define T4UFINT_ISR *((volatile unsigned long *)0x000D84) /* EV-A */
#define T4OFINT_ISR *((volatile unsigned long *)0x000D86) /* EV-A */
#define CAPINT4_ISR *((volatile unsigned long *)0x000D88) /* EV-A */
#define CAPINT5_ISR *((volatile unsigned long *)0x000D8A) /* EV-A */
#define CAPINT6_ISR *((volatile unsigned long *)0x000D8C) /* EV-A */
#define REVD5_8 *((volatile unsigned long *)0x000D8E) /* reserved */
/*-------- Group 6 PIE Interrupt Service Routines ---------------------*/
#define SPIRXINTA_ISR *((volatile unsigned long *)0x000D90) /* SPI-A RX */
#define SPITXINTA_ISR *((volatile unsigned long *)0x000D92) /* SPI-A TX */
#define REVD6_3 *((volatile unsigned long *)0x000D94) /* reserved */
#define REVD6_4 *((volatile unsigned long *)0x000D96) /* reserved */
#define MRINTA_ISR *((volatile unsigned long *)0x000D98) /* McBSP-A */
#define MXINTA_ISR *((volatile unsigned long *)0x000D9A) /* McBSP-A */
#define REVD6_7 *((volatile unsigned long *)0x000D9C) /* reserved */
#define REVD6_8 *((volatile unsigned long *)0x000D9E) /* reserved */
/*-------- Group 7 PIE Interrupt Service Routines ---------------------*/
#define REVD7_1 *((volatile unsigned long *)0x000DA0) /* reserved */
#define REVD7_2 *((volatile unsigned long *)0x000DA2) /* reserved */
#define REVD7_3 *((volatile unsigned long *)0x000DA4) /* reserved */
#define REVD7_4 *((volatile unsigned long *)0x000DA6) /* reserved */
#define REVD7_5 *((volatile unsigned long *)0x000DA8) /* reserved */
#define REVD7_6 *((volatile unsigned long *)0x000DAA) /* reserved */
#define REVD7_7 *((volatile unsigned long *)0x000DAC) /* reserved */
#define REVD7_8 *((volatile unsigned long *)0x000DAE) /* reserved */
/*-------- Group 8 PIE Interrupt Service Routines ---------------------*/
#define REVD8_1 *((volatile unsigned long *)0x000DB0) /* reserved */
#define REVD8_2 *((volatile unsigned long *)0x000DB2) /* reserved */
#define REVD8_3 *((volatile unsigned long *)0x000DB4) /* reserved */
#define REVD8_4 *((volatile unsigned long *)0x000DB6) /* reserved */
#define REVD8_5 *((volatile unsigned long *)0x000DB8) /* reserved */
#define REVD8_6 *((volatile unsigned long *)0x000DBA) /* reserved */
#define REVD8_7 *((volatile unsigned long *)0x000DBC) /* reserved */
#define REVD8_8 *((volatile unsigned long *)0x000DBE) /* reserved */
/*--------- Group 9 PIE Interrupt Service Routines ----------------------*/
#define SCIRXINTA_ISR *((volatile unsigned long *)0x000DC0) /* SCI-A RX */
#define SCITXINTA_ISR *((volatile unsigned long *)0x000DC2) /* SCI-A TX */
#define SCIRXINTB_ISR *((volatile unsigned long *)0x000DC4) /* SCI-B RX */
#define SCITXINTB_ISR *((volatile unsigned long *)0x000DC6) /* SCI-B TX */
#define ECAN0INTA_ISR *((volatile unsigned long *)0x000DC8) /* eCAN */
#define ECAN1INTA_ISR *((volatile unsigned long *)0x000DCA) /* eCAN */
#define REVD9_7 *((volatile unsigned long *)0x000DCC) /* reserved */
#define REVD9_8 *((volatile unsigned long *)0x000DCE) /* reserved */
/*-------- Group 10 PIE Interrupt Service Routines ---------------------*/
#define REVD10_1 *((volatile unsigned long *)0x000DD0) /* reserved */
#define REVD10_2 *((volatile unsigned long *)0x000DD2) /* reserved */
#define REVD10_3 *((volatile unsigned long *)0x000DD4) /* reserved */
#define REVD10_4 *((volatile unsigned long *)0x000DD6) /* reserved */
#define REVD10_5 *((volatile unsigned long *)0x000DD8) /* reserved */
#define REVD10_6 *((volatile unsigned long *)0x000DDA) /* reserved */
#define REVD10_7 *((volatile unsigned long *)0x000DDC) /* reserved */
#define REVD10_8 *((volatile unsigned long *)0x000DDE) /* reserved */
/*-------- Group 11 PIE Interrupt Service Routines ---------------------*/
#define REVD11_1 *((volatile unsigned long *)0x000DE0) /* reserved */
#define REVD11_2 *((volatile unsigned long *)0x000DE2) /* reserved */
#define REVD11_3 *((volatile unsigned long *)0x000DE4) /* reserved */
#define REVD11_4 *((volatile unsigned long *)0x000DE6) /* reserved */
#define REVD11_5 *((volatile unsigned long *)0x000DE8) /* reserved */
#define REVD11_6 *((volatile unsigned long *)0x000DEA) /* reserved */
#define REVD11_7 *((volatile unsigned long *)0x000DEC) /* reserved */
#define REVD11_8 *((volatile unsigned long *)0x000DEE) /* reserved */
/*-------- Group 12 PIE Interrupt Service Routines ---------------------*/
#define REVD12_1 *((volatile unsigned long *)0x000DF0) /* reserved */
#define REVD12_2 *((volatile unsigned long *)0x000DF2) /* reserved */
#define REVD12_3 *((volatile unsigned long *)0x000DF4) /* reserved */
#define REVD12_4 *((volatile unsigned long *)0x000DF6) /* reserved */
#define REVD12_5 *((volatile unsigned long *)0x000DF8) /* reserved */
#define REVD12_6 *((volatile unsigned long *)0x000DFA) /* reserved */
#define REVD12_7 *((volatile unsigned long *)0x000DFC) /* reserved */
#define REVD12_8 *((volatile unsigned long *)0x000DFE) /* reserved */
/*============ CPU-Timers 0, 1, 2 Configuration and Control Registers =============*/
#define TIMER0TIM *((volatile unsigned long *)0x000C00) /* CPU-Timer 0, Counter Register 32bits */
#define TIMER0TIML *((volatile unsigned int *)0x000C00) /* CPU-Timer 0, Counter Register Low */
#define TIMER0TIMH *((volatile unsigned int *)0x000C01) /* CPU-Timer 0, Counter Register High */
#define TIMER0PRD *((volatile unsigned long *)0x000C02) /* CPU-Timer 0, Period Register 32bits */
#define TIMER0PRDL *((volatile unsigned int *)0x000C02) /* CPU-Timer 0, Period Register Low */
#define TIMER0PRDH *((volatile unsigned int *)0x000C03) /* CPU-Timer 0, Period Register High */
#define TIMER0TCR *((volatile unsigned int *)0x000C04) /* CPU-Timer 0, Control Register */
/* reserved 0x000C05 */
#define TIMER0TPR *((volatile unsigned long *)0x000C06) /* CPU-Timer 0, Prescale Register 32bits */
#define TIMER0TPRL *((volatile unsigned int *)0x000C06) /* CPU-Timer 0, Prescale Register Low */
#define TIMER0TPRH *((volatile unsigned int *)0x000C07) /* CPU-Timer 0, Prescale Register High */
#define TIMER1TIM *((volatile unsigned long *)0x000C08) /* CPU-Timer 1, Counter Register 32bits */
#define TIMER1TIML *((volatile unsigned int *)0x000C08) /* CPU-Timer 1, Counter Register Low */
#define TIMER1TIMH *((volatile unsigned int *)0x000C09) /* CPU-Timer 1, Counter Register High */
#define TIMER1PRD *((volatile unsigned long *)0x000C0A) /* CPU-Timer 1, Period Register 32bits */
#define TIMER1PRDL *((volatile unsigned int *)0x000C0A) /* CPU-Timer 1, Period Register Low */
#define TIMER1PRDH *((volatile unsigned int *)0x000C0B) /* CPU-Timer 1, Period Register High */
#define TIMER1TCR *((volatile unsigned int *)0x000C0C£© /* CPU-Timer 1, Control Register */
/* reserved 0x00 0C0D */
#define TIMER1TPR *((volatile unsigned long *)0x000C0E) /* CPU-Timer 1, Prescale Register 32bits */
#define TIMER1TPRL *((volatile unsigned int *)0x000C0E) /* CPU-Timer 1, Prescale Register Low */
#define TIMER1TPRH *((volatile unsigned int *)0x000C0F) /* CPU-Timer 1, Prescale Register High */
#define TIMER2TIM *((volatile unsigned long *)0x000C10) /* CPU-Timer 2, Counter Register 32bits */
#define TIMER2TIML *((volatile unsigned int *)0x000C10) /* CPU-Timer 2, Counter Register Low */
#define TIMER2TIMH *((volatile unsigned int *)0x000C11) /* CPU-Timer 2, Counter Register High */
#define TIMER2PRD *((volatile unsigned long *)0x000C12) /* CPU-Timer 2, Period Register 32bits */
#define TIMER2PRDL *((volatile unsigned int *)0x000C12) /* CPU-Timer 2, Period Register Low */
#define TIMER2PRDH *((volatile unsigned int *)0x000C13) /* CPU-Timer 2, Period Register High */
#define TIMER2TCR *((volatile unsigned int *)0x000C14) /* CPU-Timer 2, Control Register */
/* reserved 0x00 0C15 */
#define TIMER2TPR *((volatile unsigned long *)0x000C16) /* CPU-Timer 2, Prescale Register 32bits */
#define TIMER2TPRL *((volatile unsigned int *)0x000C16) /* CPU-Timer 2, Prescale Register Low */
#define TIMER2TPRH *((volatile unsigned int *)0x000C17) /* CPU-Timer 2, Prescale Register High */
/* 0x000C18 ~ 0x000C3F 40 reserved */
/*================= ADC Registers ==============================================*/
#define ADCTRL1 *((volatile unsigned int *)0x007100) /* 1 ADC Control Register 1 */
#define ADCTRL2 *((volatile unsigned int *)0x007101) /* 1 ADC Control Register 2 */
#define ADCMAXCONV *((volatile unsigned int *)0x007102) /* 1 ADC Maximum Conversion Channels Register */
#define ADCCHSELSEQ1 *((volatile unsigned int *)0x007103) /* 1 ADC Channel Select Sequencing Control Register 1 */
#define ADCCHSELSEQ2 *((volatile unsigned int *)0x007104) /* 1 ADC Channel Select Sequencing Control Register 2 */
#define ADCCHSELSEQ3 *((volatile unsigned int *)0x007105) /* 1 ADC Channel Select Sequencing Control Register 3 */
#define ADCCHSELSEQ4 *((volatile unsigned int *)0x007106) /* 1 ADC Channel Select Sequencing Control Register 4 */
#define ADCASEQSR *((volatile unsigned int *)0x007107) /* 1 ADC Auto-Sequence Status Register */
#define ADCRESULT0 *((volatile unsigned int *)0x007108) /* 1 ADC Conversion Result Buffer Register 0 */
#define ADCRESULT1 *((volatile unsigned int *)0x007109) /* 1 ADC Conversion Result Buffer Register 1 */
#define ADCRESULT2 *((volatile unsigned int *)0x00710A) /* 1 ADC Conversion Result Buffer Register 2 */
#define ADCRESULT3 *((volatile unsigned int *)0x00710B) /* 1 ADC Conversion Result Buffer Register 3 */
#define ADCRESULT4 *((volatile unsigned int *)0x00710C) /* 1 ADC Conversion Result Buffer Register 4 */
#define ADCRESULT5 *((volatile unsigned int *)0x00710D) /* 1 ADC Conversion Result Buffer Register 5 */
#define ADCRESULT6 *((volatile unsigned int *)0x00710E) /* 1 ADC Conversion Result Buffer Register 6 */
#define ADCRESULT7 *((volatile unsigned int *)0x00710F) /* 1 ADC Conversion Result Buffer Register 7 */
#define ADCRESULT8 *((volatile unsigned int *)0x007110) /* 1 ADC Conversion Result Buffer Register 8 */
#define ADCRESULT9 *((volatile unsigned int *)0x007111) /* 1 ADC Conversion Result Buffer Register 9 */
#define ADCRESULT10 *((volatile unsigned int *)0x007112) /* 1 ADC Conversion Result Buffer Register 10 */
#define ADCRESULT11 *((volatile unsigned int *)0x007113) /* 1 ADC Conversion Result Buffer Register 11 */
#define ADCRESULT12 *((volatile unsigned int *)0x007114) /* 1 ADC Conversion Result Buffer Register 12 */
#define ADCRESULT13 *((volatile unsigned int *)0x007115) /* 1 ADC Conversion Result Buffer Register 13 */
#define ADCRESULT14 *((volatile unsigned int *)0x007116) /* 1 ADC Conversion Result Buffer Register 14 */
#define ADCRESULT15 *((volatile unsigned int *)0x007117) /* 1 ADC Conversion Result Buffer Register 15 */
#define ADCTRL3 *((volatile unsigned int *)0x007118) /* 1 ADC Control Register 3 */
#define ADCST *((volatile unsigned int *)0x007119) /* 1 ADC Status Register */
/* reserved 0x00711C ~ 0x00 711F 4 Words */
/*======================= Device Emulation Registers ================================*/
#define DEVICECNF *((volatile unsigned long *)0x000880) /* 2 Device Configuration Register */
/* reserved 0x00 0882 1 Not supported on Revision C and later silicon */
#define DEVICEID *((volatile unsigned int *)0x000883) /* 1 Device ID Register */
#define PROTSTART *((volatile unsigned int *)0x000884) /* 1 Block Protection Start Address Register */
#define PROTRANGE *((volatile unsigned int *)0x000885) /* 1 Block Protection Range Address Register */
/* reserved 0x000886 ~ 0x0009FF 378 Words */
/*===================== eCAN Registers Map ===========================*/
#define CANME *((volatile unsigned long *)0x006000) /* 1 Mailbox enable */
#define CANMD *((volatile unsigned long *)0x006002) /* 1 Mailbox direction */
#define CANTRS *((volatile unsigned long *)0x006004) /* 1 Transmit request set */
#define CANTRR *((volatile unsigned long *)0x006006) /* 1 Transmit request reset */
#define CANTA *((volatile unsigned long *)0x006008) /* 1 Transmission acknowledge */
#define CANAA *((volatile unsigned long *)0x00600A) /* 1 Abort acknowledge */
#define CANRMP *((volatile unsigned long *)0x00600C) /* 1 Receive message pending */
#define CANRML *((volatile unsigned long *)0x00600E) /* 1 Receive message lost */
#define CANRFP *((volatile unsigned long *)0x006010) /* 1 Remote frame pending */
#define CANGAM *((volatile unsigned long *)0x006012) /* 1 Global acceptance mask */
#define CANMC *((volatile unsigned long *)0x006014) /* 1 Master control */
#define CANBTC *((volatile unsigned long *)0x006016) /* 1 Bit-timing configuration */
#define CANES *((volatile unsigned long *)0x006018) /* 1 Error and status */
#define CANTEC *((volatile unsigned long *)0x00601A) /* 1 Transmit error counter */
#define CANREC *((volatile unsigned long *)0x00601C) /* 1 Receive error counter */
#define CANGIF0 *((volatile unsigned long *)0x00601E) /* 1 Global interrupt flag 0 */
#define CANGIM *((volatile unsigned long *)0x006020) /* 1 Global interrupt mask */
#define CANGIF1 *((volatile unsigned long *)0x006022) /* 1 Global interrupt flag 1 */
#define CANMIM *((volatile unsigned long *)0x006024) /* 1 Mailbox interrupt mask */
#define CANMIL *((volatile unsigned long *)0x006026) /* 1 Mailbox interrupt level */
#define CANOPC *((volatile unsigned long *)0x006028) /* 1 Overwrite protection control */
#define CANTIOC *((volatile unsigned long *)0x00602A) /* 1 TX I/O control */
#define CANRIOC *((volatile unsigned long *)0x00602C) /* 1 RX I/O control */
#define CANLNT *((volatile unsigned long *)0x00602E) /* 1 Local network time (Reserved in SCC mode) */
#define CANTOC *((volatile unsigned long *)0x006030) /* 1 Time-out control (Reserved in SCC mode) */
#define CANTOS *((volatile unsigned long *)0x006032) /* 1 Time-out status (Reserved in SCC mode) */
/* reserved 0x006033 ~ 0x006fff Words */
/*=================== EVA Registers NAME ADDRESS ===================*/
#define GPTCONA *((volatile unsigned int *)0x007400) /* 1 GP Timer Control Register A */
#define T1CNT *((volatile unsigned int *)0x007401) /* 1 GP Timer 1 Counter Register */
#define T1CMPR *((volatile unsigned int *)0x007402) /* 1 GP Timer 1 Compare Register */
#define T1PR *((volatile unsigned int *)0x007403) /* 1 GP Timer 1 Period Register */
#define T1CON *((volatile unsigned int *)0x007404) /* 1 GP Timer 1 Control Register */
#define T2CNT *((volatile unsigned int *)0x007405) /* 1 GP Timer 2 Counter Register */
#define T2CMPR *((volatile unsigned int *)0x007406) /* 1 GP Timer 2 Compare Register */
#define T2PR *((volatile unsigned int *)0x007407) /* 1 GP Timer 2 Period Register */
#define T2CON *((volatile unsigned int *)0x007408) /* 1 GP Timer 2 Control Register */
#define EXTCONA *((volatile unsigned int *)0x007409) /* 1 GP Extension Control Register A */
#define COMCONA *((volatile unsigned int *)0x007411) /* 1 Compare Control Register A */
#define ACTRA *((volatile unsigned int *)0x007413) /* 1 Compare Action Control Register A */
#define DBTCONA *((volatile unsigned int *)0x007415) /* 1 Dead-Band Timer Control Register A */
#define CMPR1 *((volatile unsigned int *)0x007417) /* 1 Compare Register 1 */
#define CMPR2 *((volatile unsigned int *)0x007418) /* 1 Compare Register 2 */
#define CMPR3 *((volatile unsigned int *)0x007419) /* 1 Compare Register 3 */
#define CAPCONA *((volatile unsigned int *)0x007420) /* 1 Capture Control Register A */
#define CAPFIFOA *((volatile unsigned int *)0x007422) /* 1 Capture FIFO Status Register A */
#define CAP1FIFO *((volatile unsigned int *)0x007423) /* 1 Two-Level Deep Capture FIFO Stack 1 */
#define CAP2FIFO *((volatile unsigned int *)0x007424) /* 1 Two-Level Deep Capture FIFO Stack 2 */
#define CAP3FIFO *((volatile unsigned int *)0x007425) /* 1 Two-Level Deep Capture FIFO Stack 3 */
#define CAP1FBOT *((volatile unsigned int *)0x007427) /* 1 Bottom Register Of Capture FIFO Stack 1 */
#define CAP2FBOT *((volatile unsigned int *)0x007428) /* 1 Bottom Register Of Capture FIFO Stack 2 */
#define CAP3FBOT *((volatile unsigned int *)0x007429) /* 1 Bottom Register Of Capture FIFO Stack 3 */
#define EVAIMRA *((volatile unsigned int *)0x00742C) /* 1 Interrupt Mask Register A */
#define EVAIMRB *((volatile unsigned int *)0x00742D) /* 1 Interrupt Mask Register B */
#define EVAIMRC *((volatile unsigned int *)0x00742E) /* 1 Interrupt Mask Register C */
#define EVAIFRA *((volatile unsigned int *)0x00742F) /* 1 Interrupt Flag Register A */
#define EVAIFRB *((volatile unsigned int *)0x007430) /* 1 Interrupt Flag Register B */
#define EVAIFRC *((volatile unsigned int *)0x007431) /* 1 Interrupt Flag Register C */
/* reserved 0x007432 ~ 0x00743F */
/*=================== EVB Registers NAME ADDRESS ===================*/
#define GPTCONB *((volatile unsigned int *)0x007500) /* 1 GP Timer Control Register b */
#define T3CNT *((volatile unsigned int *)0x007501) /* 1 GP Timer 3 Counter Register */
#define T3CMPR *((volatile unsigned int *)0x007502) /* 1 GP Timer 3 Compare Register */
#define T3PR *((volatile unsigned int *)0x007503) /* 1 GP Timer 3 Period Register */
#define T3CON *((volatile unsigned int *)0x007504) /* 1 GP Timer 3 Control Register */
#define T4CNT *((volatile unsigned int *)0x007505) /* 1 GP Timer 4 Counter Register */
#define T4CMPR *((volatile unsigned int *)0x007506) /* 1 GP Timer 4 Compare Register */
#define T4PR *((volatile unsigned int *)0x007507) /* 1 GP Timer 4 Period Register */
#define T4CON *((volatile unsigned int *)0x007508) /* 1 GP Timer 4 Control Register */
#define EXTCONB *((volatile unsigned int *)0x007509) /* 1 GP Extension Control Register B */
#define COMCONB *((volatile unsigned int *)0x007511) /* 1 Compare Control Register B */
#define ACTRB *((volatile unsigned int *)0x007513) /* 1 Compare Action Control Register B */
#define DBTCONB *((volatile unsigned int *)0x007515) /* 1 Dead-Band Timer Control Register B */
#define CMPR4 *((volatile unsigned int *)0x007517) /* 1 Compare Register 4 */
#define CMPR5 *((volatile unsigned int *)0x007518) /* 1 Compare Register 5 */
#define CMPR6 *((volatile unsigned int *)0x007519) /* 1 Compare Register 6 */
#define CAPCONB *((volatile unsigned int *)0x007520) /* 1 Capture Control Register B */
#define CAPFIFOB *((volatile unsigned int *)0x007522) /* 1 Capture FIFO Status Register B */
#define CAP4FIFO *((volatile unsigned int *)0x007523) /* 1 Two-Level Deep Capture FIFO Stack 4 */
#define CAP5FIFO *((volatile unsigned int *)0x007524) /* 1 Two-Level Deep Capture FIFO Stack 5 */
#define CAP6FIFO *((volatile unsigned int *)0x007525) /* 1 Two-Level Deep Capture FIFO Stack 6 */
#define CAP4FBOT *((volatile unsigned int *)0x007527) /* 1 Bottom Register Of Capture FIFO Stack 4 */
#define CAP5FBOT *((volatile unsigned int *)0x007528) /* 1 Bottom Register Of Capture FIFO Stack 5 */
#define CAP6FBOT *((volatile unsigned int *)0x007529) /* 1 Bottom Register Of Capture FIFO Stack 6 */
#define EVBIMRA *((volatile unsigned int *)0x00752C) /* 1 Interrupt Mask Register A */
#define EVBIMRB *((volatile unsigned int *)0x00752D) /* 1 Interrupt Mask Register B */
#define EVBIMRC *((volatile unsigned int *)0x00752E) /* 1 Interrupt Mask Register C */
#define EVBIFRA *((volatile unsigned int *)0x00752F) /* 1 Interrupt Flag Register A */
#define EVBIFRB *((volatile unsigned int *)0x007530) /* 1 Interrupt Flag Register B */
#define EVBIFRC *((volatile unsigned int *)0x007531) /* 1 Interrupt Flag Register C */
/* reserved 0x007532 ~ 0x00753F */
/*====================== GPIO Mux Registers =========================*/
#define GPAMUX *((volatile unsigned int *)0x0070C0) /* 1 GPIO A Mux Control Register */
#define GPADIR *((volatile unsigned int *)0x0070C1) /* 1 GPIO A Direction Control Register */
#define GPAQUAL *((volatile unsigned int *)0x0070C2) /* 1 GPIO A Input Qualification Control Register */
/* reserved 0x00 70C3 1 */
#define GPBMUX *((volatile unsigned int *)0x0070C4) /* 1 GPIO B Mux Control Register */
#define GPBDIR *((volatile unsigned int *)0x0070C5) /* 1 GPIO B Direction Control Register */
#define GPBQUAL *((volatile unsigned int *)0x0070C6) /* 1 GPIO B Input Qualification Control Register */
/* reserved 0x00 70C7 1 */
/* reserved 0x00 70C8 1 */
/* reserved 0x00 70C9 1 */
/* reserved 0x00 70CA 1 */
/* reserved 0x00 70CB 1 */
#define GPDMUX *((volatile unsigned int *)0x0070CC) /* 1 GPIO D Mux Control Register */
#define GPDDIR *((volatile unsigned int *)0x0070CD) /* 1 GPIO D Direction Control Register */
#define GPDQUAL *((volatile unsigned int *)0x0070CE) /* 1 GPIO D Input Qualification Control Register */
/* reserved 0x00 70CF 1 */
#define GPEMUX *((volatile unsigned int *)0x0070D0) /* 1 GPIO E Mux Control Register */
#define GPEDIR *((volatile unsigned int *)0x0070D1) /* 1 GPIO E Direction Control Register */
#define GPEQUAL *((volatile unsigned int *)0x0070D2) /* 1 GPIO E Input Qualification Control Register */
/* reserved 0x00 70D3 1 */
#define GPFMUX *((volatile unsigned int *)0x0070D4) /* 1 GPIO F Mux Control Register */
#define GPFDIR *((volatile unsigned int *)0x0070D5) /* 1 GPIO F Direction Control Register */
/* reserved 0x00 70D6 1 */
/* reserved 0x00 70D7 1 */
#define GPGMUX *((volatile unsigned int *)0x0070D8) /* 1 GPIO G Mux Control Register */
#define GPGDIR *((volatile unsigned int *)0x0070D9) /* 1 GPIO G Direction Control Register */
/* reserved 0x00 70DA 1
reserved 0x00 70DB 1
reserved 0x00 70DC ~ 0x00 70DF 4 */
/*=================== GPIO Data Registers ====================================*/
#define GPADAT *((volatile unsigned int *)0x0070E0) /* 1 GPIO A Data Register */
#define GPASET *((volatile unsigned int *)0x0070E1) /* 1 GPIO A Set Register */
#define GPACLEAR *((volatile unsigned int *)0x0070E2) /* 1 GPIO A Clear Register */
#define GPATOGGLE *((volatile unsigned int *)0x0070E3) /* 1 GPIO A Toggle Register */
#define GPBDAT *((volatile unsigned int *)0x0070E4) /* 1 GPIO B Data Register */
#define GPBSET *((volatile unsigned int *)0x0070E5) /* 1 GPIO B Set Register */
#define GPBCLEAR *((volatile unsigned int *)0x0070E6) /* 1 GPIO B Clear Register */
#define GPBTOGGLE *((volatile unsigned int *)0x0070E7) /* 1 GPIO B Toggle Register */
/* reserved 0x00 70E8 1 */
/* reserved 0x00 70E9 1 */
/* reserved 0x00 70EA 1 */
/* reserved 0x00 70EB 1 */
#define GPDDAT *((volatile unsigned int *)0x0070EC) /* 1 GPIO D Data Register */
#define GPDSET *((volatile unsigned int *)0x0070ED) /* 1 GPIO D Set Register */
#define GPDCLEAR *((volatile unsigned int *)0x0070EE) /* 1 GPIO D Clear Register */
#define GPDTOGGLE *((volatile unsigned int *)0x0070EF) /* 1 GPIO D Toggle Register */
#define GPEDAT *((volatile unsigned int *)0x0070F0) /* 1 GPIO E Data Register */
#define GPESET *((volatile unsigned int *)0x0070F1) /* 1 GPIO E Set Register */
#define GPECLEAR *((volatile unsigned int *)0x0070F2) /* 1 GPIO E Clear Register */
#define GPETOGGLE *((volatile unsigned int *)0x0070F3) /* 1 GPIO E Toggle Register */
#define GPFDAT *((volatile unsigned int *)0x0070F4) /* 1 GPIO F Data Register */
#define GPFSET *((volatile unsigned int *)0x0070F5) /* 1 GPIO F Set Register */
#define GPFCLEAR *((volatile unsigned int *)0x0070F6) /* 1 GPIO F Clear Register */
#define GPFTOGGLE *((volatile unsigned int *)0x0070F7) /* 1 GPIO F Toggle Register */
#define GPGDAT *((volatile unsigned int *)0x0070F8) /* 1 GPIO G Data Register */
#define GPGSET *((volatile unsigned int *)0x0070F9) /* 1 GPIO G Set Register */
#define GPGCLEAR *((volatile unsigned int *)0x0070FA) /* 1 GPIO G Clear Register */
#define GPGTOGGLE *((volatile unsigned int *)0x0070FB) /* 1 GPIO G Toggle Register */
/* reserved 0x00 70FC ~ 0x00 70FF */
/*================== McBSP Register Summary ============================*/
/* DATA REGISTERS, RECEIVE, TRANSMIT */
/* NAME ADDRESS(0x0078xxh) TYPE(R/W) RESET VALUE DESCRIPTION */
/* 0x0000 McBSP Receive Buffer Register
0x0000 McBSP Receive Shift Register
0x0000 McBSP Transmit Shift Register
*/
#define DRR2 *((volatile unsigned int *)0x007800) /* R 0x0000 McBSP Data Receive Register 2, */
/* read First if the word size is greater than 16 bits,
else ignore DRR2 */
#define DRR1 *((volatile unsigned int *)0x007801) /* R 0x0000 McBSP Data Receive Register 1 */
/* Read Second if the word size is greater than 16 bits,
else read DRR1 only */
#define DXR2 *((volatile unsigned int *)0x007802) /* W 0x0000 McBSP Data Transmit Register 2 */
/* Write First if the word size is greater than 16 bits,
else ignore DXR2 */
#define DXR1 *((volatile unsigned int *)0x007803) /* W 0x0000 McBSP Data Transmit Register 1 */
/* Write Second if the word size is greater than 16 bits,
else write to DXR1 only */
/*================= McBSP CONTROL REGISTERS ==============================*/
#define SPCR2 *((volatile unsigned int *)0x007804) /* R/W 0x0000 McBSP Serial Port Control Register 2 */
#define SPCR1 *((volatile unsigned int *)0x007805) /* R/W 0x0000 McBSP Serial Port Control Register 1 */
#define RCR2 *((volatile unsigned int *)0x007806) /* R/W 0x0000 McBSP Receive Control Register 2 */
#define RCR1 *((volatile unsigned int *)0x007807) /* R/W 0x0000 McBSP Receive Control Register 1 */
#define XCR2 *((volatile unsigned int *)0x007808) /* R/W 0x0000 McBSP Transmit Control Register 2 */
#define XCR1 *((volatile unsigned int *)0x007809) /* R/W 0x0000 McBSP Transmit Control Register 1 */
#define SRGR2 *((volatile unsigned int *)0x00780A) /* R/W 0x0000 McBSP Sample Rate Generator Register 2 */
#define SRGR1 *((volatile unsigned int *)0x00780B) /* R/W 0x0000 McBSP Sample Rate Generator Register 1 */
/*===================== MULTICHANNEL CONTROL REGISTERS ==========================================*/
#define MCR2 *((volatile unsigned int *)0x00780C) /* R/W 0x0000 McBSP Multichannel Register 2 */
#define MCR1 *((volatile unsigned int *)0x00780D) /* R/W 0x0000 McBSP Multichannel Register 1 */
#define RCERA *((volatile unsigned int *)0x00780E) /* R/W 0x0000 McBSP Receive Channel Enable Register Partition A */
#define RCERB *((volatile unsigned int *)0x00780F) /* R/W 0x0000 McBSP Receive Channel Enable Register Partition B */
#define XCERA *((volatile unsigned int *)0x007810) /* R/W 0x0000 McBSP Transmit Channel Enable Register Partition A */
#define XCERB *((volatile unsigned int *)0x007811) /* R/W 0x0000 McBSP Transmit Channel Enable Register Partition B */
#define PCR1 *((volatile unsigned int *)0x007812) /* R/W 0x0000 McBSP Pin Control Register */
#define RCERC *((volatile unsigned int *)0x007813) /* R/W 0x0000 McBSP Receive Channel Enable Register Partition C */
#define RCERD *((volatile unsigned int *)0x007814) /* R/W 0x0000 McBSP Receive Channel Enable Register Partition D */
#define XCERC *((volatile unsigned int *)0x007815) /* R/W 0x0000 McBSP Transmit Channel Enable Register Partition C */
#define XCERD *((volatile unsigned int *)0x007816) /* R/W 0x0000 McBSP Transmit Channel Enable Register */
/*================== SCI-A Registers =======================================*/
#define SCICCRA *((volatile unsigned int *)0x007050) /* 1 SCI-A Communications Control Register */
#define SCICTL1A *((volatile unsigned int *)0x007051) /* 1 SCI-A Control Register 1 */
#define SCIHBAUDA *((volatile unsigned int *)0x007052) /* 1 SCI-A Baud Register, High Bits */
#define SCILBAUDA *((volatile unsigned int *)0x007053) /* 1 SCI-A Baud Register, Low Bits */
#define SCICTL2A *((volatile unsigned int *)0x007054) /* 1 SCI-A Control Register 2 */
#define SCIRXSTA *((volatile unsigned int *)0x007055) /* 1 SCI-A Receive Status Register */
#define SCIRXEMUA *((volatile unsigned int *)0x007056) /* 1 SCI-A Receive Emulation Data Buffer Register */
#define SCIRXBUFA *((volatile unsigned int *)0x007057) /* 1 SCI-A Receive Data Buffer Register */
#define SCITXBUFA *((volatile unsigned int *)0x007059) /* 1 SCI-A Transmit Data Buffer Register */
#define SCIFFTXA *((volatile unsigned int *)0x00705A) /* 1 SCI-A FIFO Transmit Register */
#define SCIFFRXA *((volatile unsigned int *)0x00705B) /* 1 SCI-A FIFO Receive Register */
#define SCIFFCTA *((volatile unsigned int *)0x00705C) /* 1 SCI-A FIFO Control Register */
#define SCIPRIA *((volatile unsigned int *)0x00705F) /* 1 SCI-A Priority Control Register */
/*================= SCI-B Registers =====================================*/
#define SCICCRB *((volatile unsigned int *)0x007750) /* 1 SCI-B Communications Control Register */
#define SCICTL1B *((volatile unsigned int *)0x007751) /* 1 SCI-B Control Register 1 */
#define SCIHBAUDB *((volatile unsigned int *)0x007752) /* 1 SCI-B Baud Register, High Bits */
#define SCILBAUDB *((volatile unsigned int *)0x007753) /* 1 SCI-B Baud Register, Low Bits */
#define SCICTL2B *((volatile unsigned int *)0x007754) /* 1 SCI-B Control Register 2 */
#define SCIRXSTB *((volatile unsigned int *)0x007755) /* 1 SCI-B Receive Status Register */
#define SCIRXEMUB *((volatile unsigned int *)0x007756) /* 1 SCI-B Receive Emulation Data Buffer Register */
#define SCIRXBUFB *((volatile unsigned int *)0x007757) /* 1 SCI-B Receive Data Buffer Register */
#define SCITXBUFB *((volatile unsigned int *)0x007759) /* 1 SCI-B Transmit Data Buffer Register */
#define SCIFFTXB *((volatile unsigned int *)0x00775A) /* 1 SCI-B FIFO Transmit Register */
#define SCIFFRXB *((volatile unsigned int *)0x00775B) /* 1 SCI-B FIFO Receive Register */
#define SCIFFCTB *((volatile unsigned int *)0x00775C) /* 1 SCI-B FIFO Control Register */
#define SCIPRIB *((volatile unsigned int *)0x00775F) /* 1 SCI-B Priority Control Register */
/*==================== SPI Registers ============================================*/
#define SPICCR *((volatile unsigned int *)0x007040) /* 1 SPI Configuration Control Register */
#define SPICTL *((volatile unsigned int *)0x007041) /* 1 SPI Operation Control Register */
#define SPISTS *((volatile unsigned int *)0x007042) /* 1 SPI Status Register */
#define SPIBRR *((volatile unsigned int *)0x007044) /* 1 SPI Baud Rate Register */
#define SPIRXEMU *((volatile unsigned int *)0x007046) /* 1 SPI Receive Emulation Buffer Register */
#define SPIRXBUF *((volatile unsigned int *)0x007047) /* 1 SPI Serial Input Buffer Register */
#define SPITXBUF *((volatile unsigned int *)0x007048) /* 1 SPI Serial Output Buffer Register */
#define SPIDAT *((volatile unsigned int *)0x007049) /* 1 SPI Serial Data Register */
#define SPIFFTX *((volatile unsigned int *)0x00704A) /* 1 SPI FIFO Transmit Register */
#define SPIFFRX *((volatile unsigned int *)0x00704B) /* 1 SPI FIFO Receive Register */
#define SPIFFCT *((volatile unsigned int *)0x00704C) /* 1 SPI FIFO Control Register */
#define SPIPRI *((volatile unsigned int *)0x00704F) /* 1 SPI Priority Control Register */
/*============== XINTF Configuration and Control Register Mappings ===============*/
#define XTIMING0 *((volatile unsigned long *)0x000B20) /* 2 XINTF Timing Register, Zone 0 can access as two 16-bit registers or one 32-bit register */
#define XTIMING1 *((volatile unsigned long *)0x000B22) /* 2 XINTF Timing Register, Zone 1 can access as two 16-bit registers or one 32-bit register */
#define XTIMING2 *((volatile unsigned long *)0x000B24) /* 2 XINTF Timing Register, Zone 2 can access as two 16-bit registers or one 32-bit register */
#define XTIMING6 *((volatile unsigned long *)0x000B2C) /* 2 XINTF Timing Register, Zone 6 can access as two 16-bit registers or one 32-bit register */
#define XTIMING7 *((volatile unsigned long *)0x000B2E) /* 2 XINTF Timing Register, Zone 7 can access as two 16-bit registers or one 32-bit register */
#define XINTCNF2 *((volatile unsigned long *)0x000B34) /* 2 XINTF Configuration Register can access as two 16-bit registers or one 32-bit register */
#define XBANK *((volatile unsigned int *)0x000B38) /* 1 XINTF Bank Control Register */
#define XREVISION *((volatile unsigned int *)0x000B3A) /* 1 XINTF Revision Register */
/*================== External Interrupts Registers ============================*/
#define XINT1CR *((volatile unsigned int *)0x007070) /* 1 XINT1 control register */
#define XINT2CR *((volatile unsigned int *)0x007071) /* 1 XINT2 control register */
/* reserved 0x00 7072 ~ 0x00 7076 5 */
#define XNMICR *((volatile unsigned int *)0x007077) /* 1 XNMI control register */
#define XINT1CTR *((volatile unsigned int *)0x007078) /* 1 XINT1 counter register */
#define XINT2CTR *((volatile unsigned int *)0x007079) /* 1 XINT2 counter register */
/* reserved 0x00 707A ~ 0x00 707E 5 */
#define XNMICTR *((volatile unsigned int *)0x00707F) /* 1 XNMI counter register */
#endif