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--The IEEE standard 1164 package, declares std_logic, rising_edge(), etc. 
library IEEE; 
use IEEE.std_logic_1164.all; 
use IEEE.std_logic_arith.all; 
use IEEE.std_logic_unsigned.all; 
entity i60bcd is 
  port (interg : in integer range 0 to 59;--interger number 
           ten : out std_logic_vector (3 downto 0) ;--decimal bit 
           one : out std_logic_vector (3 downto 0) );--individual bit 
end i60bcd; 
architecture arch of i60bcd is 
begin 
  process(interg) 
  begin 
    case interg is 
      when 0|10|20|30|40|50 => one<="0000"; 
      when 1|11|21|31|41|51 => one<="0001"; 
      when 2|12|22|32|42|52 => one<="0010"; 
      when 3|13|23|33|43|53 => one<="0011"; 
      when 4|14|24|34|44|54 => one<="0100"; 
      when 5|15|25|35|45|55 => one<="0101"; 
      when 6|16|26|36|46|56 => one<="0110"; 
      when 7|17|27|37|47|57 => one<="0111"; 
      when 8|18|28|38|48|58 => one<="1000"; 
      when 9|19|29|39|49|59 => one<="1001"; 
      when others           => one<="1110"; 
    end case; 
    case interg is 
      when 0|1|2|3|4|5|6|7|8|9 => ten<="0000"; 
      when 10|11|12|13|14|15|16|17|18|19 => ten<="0001"; 
      when 20|21|22|23|24|25|26|27|28|29 => ten<="0010"; 
      when 30|31|32|33|34|35|36|37|38|39 => ten<="0011"; 
      when 40|41|42|43|44|45|46|47|48|49 => ten<="0100"; 
      when 50|51|52|53|54|55|56|57|58|59 => ten<="0101"; 
      when others           => ten<="1110"; 
    end case; 
  end process; 
end arch;