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--fadd4.vhd 4-bit ripple-carry adder 
library ieee ; 
use ieee.std_logic_1164.all; 
use work.components.all; 
entity fadd4 is 
port( 
  	a	: in std_logic_vector(3 downto 0);--被加數 
	b 	: in std_logic_vector(3 downto 0);--加數 
  	ci 	: in std_logic;--進位輸入 
  	co 	: out std_logic;--進位輸出 
  	sum : out std_logic_vector(3 downto 0));--和 
end fadd4; 
architecture behavior of fadd4 is  
  signal ci_ns : std_logic_vector(2 downto 0);--ci與co的連線 
begin  
  u0: fadd  port map (a(0),b(0),ci,ci_ns(0),sum(0)); 
  u1: fadd  port map (a(1),b(1),ci_ns(0),ci_ns(1),sum(1)); 
  u2: fadd  port map (a(2),b(2),ci_ns(1),ci_ns(2),sum(2)); 
  u3: fadd  port map (a(3),b(3),ci_ns(2),co,sum(3)); 
end behavior;