www.pudn.com > codeofvhdl2006.rar > FADD.VHD

--fadd.vhd fadd.vhd one bit full adder 
library ieee ; 
use ieee.std_logic_1164.all; 
entity fadd is 
port( 
  a: in std_logic;--被加數 
  b: in std_logic;---加數 
  ci : in std_logic;--進位輸入 
  co: out std_logic; --進位輸出 
  sum : out std_logic);--和 
end fadd; 
architecture behavior of fadd is  
begin  
  co<=(a and b) or (b and ci) or (a and ci); 
  sum<=a xor b xor ci; 
end behavior;