www.pudn.com > codeofvhdl2006.rar > DOWNCNT.VHD

--downcnt.vhd n modules downcounter 
library ieee ; 
use ieee.std_logic_1164.all ; 
entity downcnt is 
generic ( modulus : integer := 8 ) ; 
port ( 
	clock : in std_logic ; 
	e : in std_logic ;--enable 1->enable 0->disable 
	l : in std_logic ;--load 1->load 
	q : out	integer range 0 to modulus-1 ) ; 
end downcnt ; 
architecture behavior of downcnt is 
	signal count : integer range 0 to modulus-1 ; 
begin 
  process 
  begin 
    wait until (clock'event and clock = '1') ;--clock positive edge trigger 
	  if e = '1' then 
		if l = '1' then 
          count <= modulus-1 ;--loading 
		else 
		  count <= count-1 ;--counting 
		end if ; 
	end if ; 
  end process; 
	q <= count ;--output internal signal 
end behavior ;