www.pudn.com > codeofvhdl2006.rar > DIV1024.VHD

Library IEEE; 
Use IEEE.std_logic_1164.all; 
Use ieee.std_logic_unsigned.all; 
Use IEEE.std_logic_arith.all; 
Entity div1024 is 
  Port( clk: in std_logic;--from system clock(1024Hz) 
       f1hz: out std_logic);-- 1Hz output signal 
end div1024; 
architecture arch of div1024 is 
--input: clk 
--output: f1hz 
  signal count : integer range 0 to 1023;--count from 0 to 1023-local signal 
begin 
----process for dividing by 1024 
process (clk) 
begin 
  if rising_edge(clk) then 
     count<=count+1; 
     if count>=63 then f1hz<='1'; 
                  else f1hz<='0';  
     end if; 
  end if; 
end process; 
end arch;