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Library IEEE; 
Use IEEE.std_logic_1164.all; 
Use ieee.std_logic_unsigned.all; 
Use IEEE.std_logic_arith.all; 
Entity count24 is 
  Port(carry: in std_logic;--from 1Hz input clock or the full_index of second/minute 
         Rst: in std_logic;--initialization 
       times: out integer range 0 to 23; 
        full: out std_logic);-- carry_out signal 
end count24; 
architecture arch of count24 is 
--input:rst,carry 
--output:times,full 
  signal time : integer range 0 to 23; 
begin 
----process for 60 seconds counting 
  process (rst,carry) 
  begin 
    if rst='1' then time <= 0; full<='0'; 
    elsif rising_edge(carry) then 
          if time=23 then time<=0;--over 24 
                          full<='1';--carry_out signal 
                     else time<= time + 1;--keep counting  
                          full<='0'; 
          end if;      
    end if; 
  end process; 
  times<=time; 
end arch;