www.pudn.com > codeofvhdl2006.rar > CLK_GEN.VHD

--library declaration 
library IEEE; 
use IEEE.std_logic_1164.all; 
use IEEE.std_logic_arith.all; 
use IEEE.std_logic_unsigned.all; 
--input and output pins declaraction 
entity clk_gen is 
    port(reset: in std_logic; 
         clk:in std_logic; 
         ena_scan:out std_logic; 
         ena_1Hz:out std_logic; 
         flash_1Hz: out std_logic); 
end;    
 
architecture BEHAVIOR of clk_gen is    
CONSTANT scan_bit: positive := 2; 
CONSTANT scan_val: positive := 4; 
CONSTANT two_Hz_bit: positive := 7; 
CONSTANT two_Hz_val: positive := 125; 
signal clk_scan_ff:std_logic_vector(scan_bit-1 downto 0);  
signal clk_2Hz_ff:std_logic_vector(two_Hz_bit-1 downto 0);  
signal ena_s,ena_one,ena_two:std_logic; 
begin 
--to generate 250Hz ena_s via dividing 1KHz clock by 4 
   scan:process(reset,clk) 
   begin 
       if reset='1' then 
          clk_scan_ff<="00"; 
          ena_s<='0'; 
       elsif (clk'event and clk='1') then 
          if clk_scan_ff>=scan_val-1 then 
             clk_scan_ff<="00"; 
             ena_s <= '1'; 
          else 
             clk_scan_ff<=clk_scan_ff+1;   
             ena_s <= '0'; 
          end if; 
       end if; 
   end process;   
ena_scan <= ena_s; 
--to generate 1Hz ena_1Hz and flash_1Hz via dividing 1KHz clock by 
   two_Hz:process(reset,clk,ena_s) 
   begin 
       if reset='1' then 
          ena_one<='0'; 
          ena_two<='0'; 
          clk_2Hz_ff<="0000000"; 
       elsif (clk'event and clk='1') then 
          if ena_s='1' then 
            if clk_2Hz_ff>=two_Hz_val-1 then 
               clk_2Hz_ff<="0000000"; 
               ena_two <= '1'; 
               ena_one <= not ena_one; 
            else 
               clk_2Hz_ff<=clk_2Hz_ff+1;   
               ena_two <= '0'; 
               ena_one <= ena_one; 
            end if; 
          end if; 
       end if; 
   end process;  
ena_1Hz <= ena_one and ena_two and ena_s; 
flash_1Hz <= ena_one; 
end BEHAVIOR;