www.pudn.com > codeofvhdl2006.rar > CAL.VHD, change:2001-08-10,size:6251b
----libray and package declaraction
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.my_pkg.all;
Entity clock is
Port(rst: in std_logic;--power reset to initialize
clk: in std_logic;--system clock 1024Hz
alarm: in std_logic;--dip switch for alarm setting
stop: in std_logic;--dip switch for stop watch setting
Ok: in std_logic;--push button to confirrn any setting operation
Sec_tune: in std_logic;--pushing button to tune seconds
Min_tune: in std_logic;--pushing button to tune minutes
Hour_tune: in std_logic;--pushing button to tune hourss
led_alarm: out std_logic;--led to show alarm time reached
led_stop: out std_logic;--led to show count_down over
seg4: out std_logic_vector(6 downto 0);--display seconds and minutes
p1,p2,p3,p4: out std_logic;--power for sec_one,sec_ten,min_one and min_ten
seg2: out std_logic_vector(6 downto 0);--display hours
p5,p6: out std_logic);--power for hour_one,hour_ten
End clock;
architecture arch of clock is
--global signals flowing among different circuit blocks
signal Hz1:std_logic;--1 Hz clock
--normal dispay time
signal n_sec,n_min: integer range 0 to 59;
signal n_hour: integer range 0 to 23;
--alarm display time
signal a_sec,a_min: integer range 0 to 59;
signal a_hour: integer range 0 to 23;
--stop display time
signal s_sec,s_min: integer range 0 to 59;
signal s_hour: integer range 0 to 23;
--chosen display time
signal second,minute :integer range 0 to 59;
signal hour :integer range 0 to 23;
signal sec_one,sec_ten,min_one,min_ten: std_logic_vector(3 downto 0);
signal hour_one,hour_ten: std_logic_vector(3 downto 0);
--chosen display time in 7-segments led format
signal sec7_one,sec7_ten,min7_one,min7_ten: std_logic_vector(6 downto 0);
signal hour7_one,hour7_ten: std_logic_vector(6 downto 0);
--index for alarm or stop_watch status
signal stop_index,alarm_index: std_logic;
signal alarm_disp,stop_disp : std_logic;
begin
----normal counting from 00:00:00 to 23:59:59
normal_counting:Block
--input : rst,clk
--output: Hz1, n_sec,n_min,n_hour
signal full_sec:std_logic;--index of 60 seconds fully counted
signal full_min:std_logic;--index of 60 minutes fully counted
signal full_hour:std_logic;--index of 24 hours fully counted
begin
--to get 1Hz clock
u0:div1024 port map(clk=>clk,f1hz=>Hz1);
--to count from 0 to 60 seconds and get full_sec
u1:count60 port map(rst=>rst,carry=>hz1,times=>n_sec,full=>full_sec);
--to count from 0 to 60 minutes and get full_min
u2:count60 port map(rst=>rst,carry=>full_sec,times=>n_min,full=>full_min);
--to count from 0 to 24 hours and get full_hour
u3:count24 port map(rst=>rst,carry=>full_min,times=>n_hour,full=>full_hour);
end block normal_counting;
----stop watch setting and down_counting
stop_w: block
--input:rst,hz1,stop,ok,sec_tune,min_tune,hour_tune
--output:s_sec,s_min,s_hour,stop_index
begin
u4:stop_watch port MAP(rst=>rst,hz1=>hz1,stop=>stop,ok=>ok,sec_tune=>sec_tune,
min_tune=>min_tune,hour_tune=>hour_tune,stop_sec=>s_sec,
stop_min=>s_min,stop_hour=>s_hour,index=>stop_index,disp=>stop_disp);
p1:process(rst,stop_index)
begin
if rst='1' then led_stop<='0';
elsif rising_edge(stop_index) then
led_stop<='1';
end if;
end process p1;
end block stop_w;
alarm_setting:Block
--input : rst,sec_tune,min_tune,hour_tune,alarm,ok
--output: a_sec,a_min,a_hour,alarm_index,led_alarm
begin
u5:alarm_set port map(rst=>rst,hz1=>hz1,alarm=>alarm,ok=>ok,sec_tune=>sec_tune,
min_tune=>min_tune,hour_tune=>hour_tune,
sec=>a_sec,min=>a_min,hour=>a_hour);
p1:process(alarm,ok)
begin
if rst='1' then alarm_index<='0';
elsif alarm='1' and ok='1' then
if (a_sec=n_sec and a_min=n_min and a_hour=n_hour)
then alarm_index<='1';
else alarm_index<='0';
end if;
end if;
alarm_disp<=(alarm and not ok) and not alarm_index;
end process p1;
p2:process(rst,alarm_index)
begin
if rst='1' then led_alarm<='0';
elsif rising_edge(alarm_index) then
led_alarm<='1';
end if;
end process p2;
end block alarm_setting;
----to decide which time displayed and transform to BCD format
output:block
--input:clk,stop_disp,alarm_disp
--input:s_sec,s_min,s_hour,a_sec,a_min,a_hour,n_sec,n_min,n_hour
--output:second,minute,hour
begin
process(clk,stop_disp,alarm_disp)
begin
if rising_edge(clk) then
if stop_disp='1' then second<=s_sec;
minute<=s_min;
hour<=s_hour;
elsif alarm_disp='1' then second<=a_sec;
minute<=a_min;
hour<=a_hour;
else second<=n_sec;
minute<=n_min;
hour<=n_hour;
end if;
end if;
end process;
----tranformed to BCD format
u6:i60bcd port MAP(interg=>second,ten=>sec_ten,one=>sec_one);
u7:i60bcd port MAP(interg=>minute,ten=>min_ten,one=>min_one);
u8:i24bcd port MAP(interg=>hour,ten=>hour_ten,one=>hour_one);
end block output;
---transform BCD format to 7_segment LED display format and scan out
scan_display:block
begin
u11:bin2led port map(bin=>sec_one,led=>sec7_one);
u12:bin2led port map(bin=>sec_ten,led=>sec7_ten);
u13:bin2led port map(bin=>min_one,led=>min7_one);
u14:bin2led port map(bin=>min_ten,led=>min7_ten);
u15:bin2led port map(bin=>hour_one,led=>hour7_one);
u16:bin2led port map(bin=>hour_ten,led=>hour7_ten);
u17:scan4 port map(rst=>rst,clk=>clk,
a=>sec7_one,b=>sec7_ten,c=>min7_one,d=>min7_ten,
mux_out=>seg4,pa=>p1,pb=>p2,pc=>p3,pd=>p4);
u18: scan2 port map(rst=>rst,clk=>clk,
a=>hour7_one,b=>hour7_ten,mux_out=>seg2,pa=>p5,pb=>p6);
end block scan_display;
end arch;