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--bcd3.vhd	3 digits bcd adder/subtractor 
library ieee ; 
use ieee.std_logic_1164.all; 
use work.components.all; 
entity bcd3 is 
port( 
  a	  : in std_logic_vector(11 downto 0);--被加／減數 
  b	  : in std_logic_vector(11 downto 0);--加／減數 
  ci  :	in std_logic;--進位輸入 
  sel : in std_logic;--加／減法模式選擇，0=>加法，1=>減法 
  co  : out std_logic;--進位輸出 
  sum : out std_logic_vector(11 downto 0));--和 
end bcd3; 
architecture behavior of bcd3 is  
  signal cc : std_logic_vector(1 downto 0);--bcd.co ->bcd.ci interconnetcion 
begin 
  bcd1: bcd port map (a(3 downto 0), b(3 downto 0), ci, sel, cc(0), sum(3 downto 0)) ; 
  bcd2: bcd port map (a(7 downto 4), b(7 downto 4), cc(0), sel, cc(1), sum(7 downto 4)) ; 
  bcd3: bcd port map (a(11 downto 8), b(11 downto 8), cc(1), sel, co, sum(11 downto 8)) ; 
end behavior;