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----libray and package declaraction 
library IEEE; 
use IEEE.std_logic_1164.all; 
use IEEE.std_logic_arith.all; 
use IEEE.std_logic_unsigned.all; 
Entity alarm_set is 
  Port(rst,hz1: in std_logic;--system clock 1Hz 
       alarm,ok: in std_logic;--keep pushing to declare alarm set 
       sec_tune: in std_logic;-- keep pushing to declare second tuning 
       min_tune: in std_logic;-- keep pushing to declare minute tuning 
       hour_tune: in std_logic; --keep pushing to declare hour tuning 
       sec,min: out integer range 0 to 59; 
       hour: out integer range 0 to 23); 
End; 
----define the signal_structure and _flow of the device  
architecture arch of alarm_set is 
  signal sec_tmp,min_tmp:  integer range 0 to 59; 
  signal hour_tmp:  integer range 0 to 23;    
begin 
  tuning:process(rst,hz1,alarm,ok) 
  begin 
  if rst='1' then sec_tmp<=0; min_tmp<=0; hour_tmp<=0; 
  elsif rising_edge(hz1) then 
      if alarm='1' and ok='0' then 
           if sec_tune='1' then  
              if sec_tmp=59 then sec_tmp<=0; 
                          else sec_tmp<=sec_tmp + 1; 
              end if; 
           end if; 
           if min_tune='1' then  
              if min_tmp=59 then min_tmp<=0; 
                          else min_tmp<=min_tmp + 1; 
              end if; 
           end if; 
           if hour_tune='1' then 
              if hour_tmp=23 then hour_tmp<=0; 
                           else hour_tmp<=hour_tmp + 1; 
              end if; 
           end if; 
      else 
          null; 
      end if; 
  end if; 
  end process tuning; 
    sec<=sec_tmp; 
    min<=min_tmp; 
    hour<=hour_tmp; 
end arch;