www.pudn.com > dds_quicklogic.zip > SINLUP.V

/******************************************************************************* 
 **						         c : CelLogic, 1996 
 ** 
 ** The information contained herein is proprietary of CelLogic. 
 ** Any reproduction, in whole or part, disclosure, or use of this code is 
 ** expressly prohibited except as specified in writing by CelLogic. 
 **************************************************************************** 
 **                                                                              
 **                                                                              
 ** Project Name         : DDS                                             
 **                                                                              
 ** Author               : Daniel J. Morelli 
 ** Creation Date        : 03/04/96 20:33:07                                               
 ** Version Number       : 1.0                                                  
 **                                                                              
 ** Revision History     :                                                       
 **                                                                              
 ** Date          Initials         Modification                                  
 **                                                                              
 **                                                                              
 ** Description          :                                                       
 **                                                                              
 ** This block takes the phase angle value and outputs the sin wave 
 ** value to the DAC.  This module looks up the sin wave values stored 
 ** as a 1/4 sin wave in the romtab module. 
 **  
 **                                                                              
 *******************************************************************************/ 
 
 module sinlup ( 
	SYSCLK,			// system clock input 
	RESETN,			// global reset 
	MODPHASE,		// modulated phase output 
	DACOUT);			// DAC output of sin wave 
 
// Port types 
 
input SYSCLK, RESETN; 
input[7:0] MODPHASE; 
 
output[7:0] DACOUT; 
 
reg[5:0] phaseadd;	// 1/4 wave phase address to ROM table 
reg modphase_msb1_ff;		// modulated phase MSB 
reg modphase_msb2_ff;		// modulated phase MSB 
reg[7:0] dac_ff;		// registered DAC output 
wire[6:0] qwavesin;	// 1/4 wave sin value from ROM table 
reg [6:0] qwavesin_ff;	// rom table output registered 
 
// design architecture 
	assign DACOUT = dac_ff; 
 
  	romtab U_romtab(phaseadd, qwavesin); 
  
   // get the phase angle for 1/4 rom table 
	always @(posedge SYSCLK or negedge RESETN) 
		if (!RESETN) 
		begin 
			phaseadd <= 6'h00; 
			modphase_msb1_ff <= 0; 
			modphase_msb2_ff <= 0; 
			qwavesin_ff <= 7'h00; 
			dac_ff <= 8'h00; 
		end 
		else 
		begin 
			modphase_msb1_ff <= MODPHASE[7]; 
			modphase_msb2_ff <= modphase_msb1_ff; 
			qwavesin_ff <= qwavesin; 
			if (MODPHASE[6]) 
				phaseadd <= ~MODPHASE[5:0]; 
			else 
				phaseadd <= MODPHASE[5:0]; 
			dac_ff[7] <= ~modphase_msb2_ff; 
			if (modphase_msb2_ff) 
				dac_ff[6:0] <= ~qwavesin_ff; 
			else 
				dac_ff[6:0] <= qwavesin_ff; 
		end 
 
 
endmodule