www.pudn.com > dds_quicklogic.zip > ROMTAB.V

/******************************************************************************* 
**************************************************************************** 
 **                                                                              
 **                                                                              
 ** Project Name         : DDS                                             
 **                                                                              
 ** Author               : Daniel J. Morelli 
 ** Creation Date        : 03/04/96 18:20:21                                               
 ** Version Number       : 1.0                                                  
 **                                                                              
 ** Revision History     :                                                       
 **                                                                              
 ** Date          Initials         Modification                                  
 **                                                                              
 **                                                                              
 ** Description          :                                                       
 **                                                                              
 ** This ,module is the 1/4 wave sin lookup table.  The input to the block is 
 ** the phase angle value and the output is the 8 bit sin value. 
 **  
 **                                                                              
 *******************************************************************************/ 
 
 module romtab ( 
	PHASEADD,		// phase address value 
	QWAVESIN);		// 1/4 wave sin value 
 
// Port types 
 
input[5:0] PHASEADD; 
 
output[6:0] QWAVESIN; 
 
reg[6:0]	sinrom;				// sine wave ROM 
 
// design architecture 
	assign QWAVESIN = sinrom; 
 
	always @(PHASEADD) 
	case (PHASEADD) 
		6'd0:		sinrom = 7'd0;			// 0.0 
		6'd1:	 	sinrom = 7'd3;			//3.12 
		6'd2:	 	sinrom = 7'd6;			//6.23 
		6'd3:	 	sinrom = 7'd9;			//9.34 
		6'd4:	 	sinrom = 7'd12;			//12.44 
		6'd5:	 	sinrom = 7'd16;			//15.55 
		6'd6:	 	sinrom = 7'd19;			//18.63 
		6'd7:	 	sinrom = 7'd22;			//21.71 
		6'd8:	 	sinrom = 7'd25;			//24.78 
		6'd9:	 	sinrom = 7'd28;			//27.82 
		6'd10:	 	sinrom = 7'd31;			//30.86 
		6'd11:	 	sinrom = 7'd34;			//33.87 
		6'd12:	 	sinrom = 7'd37;			//36.87 
		6'd13:	 	sinrom = 7'd40;			//39.84 
		6'd14:	 	sinrom = 7'd43;			//42.79 
		6'd15:	 	sinrom = 7'd46;			//45.71 
		6'd16:	 	sinrom = 7'd49;			//48.60 
		6'd17:	 	sinrom = 7'd51;			//51.47 
		6'd18:	 	sinrom = 7'd54;			//54.30 
		6'd19:	 	sinrom = 7'd57;			//57.10 
		6'd20:	 	sinrom = 7'd60;			//59.87 
		6'd21:	 	sinrom = 7'd63;			//62.60 
		6'd22:	 	sinrom = 7'd65;			//65.29 
		6'd23:	 	sinrom = 7'd68;			//67.94 
		6'd24:	 	sinrom = 7'd71;			//70.56 
		6'd25:	 	sinrom = 7'd73;			//73.13 
		6'd26:	 	sinrom = 7'd76;			//75.65 
		6'd27:	 	sinrom = 7'd78;			//78.13 
		6'd28:	 	sinrom = 7'd81;			//80.57 
		6'd29:	 	sinrom = 7'd83;			//82.95 
		6'd30:	 	sinrom = 7'd85;			//85.29 
		6'd31:	 	sinrom = 7'd88;			//87.57 
		6'd32:	 	sinrom = 7'd90;			//89.80 
		6'd33:	 	sinrom = 7'd92;			//91.98 
		6'd34:	 	sinrom = 7'd94;			//94.10 
		6'd35:	 	sinrom = 7'd96;			//96.17 
		6'd36:	 	sinrom = 7'd98;			//98.17 
		6'd37:	 	sinrom = 7'd100;		//100.11 
		6'd38:	 	sinrom = 7'd102;			//102.01 
		6'd39:	 	sinrom = 7'd104;			//103.83 
		6'd40:	 	sinrom = 7'd106;			//105.60 
		6'd41:	 	sinrom = 7'd107;			//107.30 
		6'd42:	 	sinrom = 7'd109;			//108.93 
		6'd43:	 	sinrom = 7'd111;			//110.50 
		6'd44:	 	sinrom = 7'd112;			//112.00 
		6'd45:	 	sinrom = 7'd113;			//113.44 
		6'd46:	 	sinrom = 7'd115;			//114.81 
		6'd47:	 	sinrom = 7'd116;			//116.10 
		6'd48:	 	sinrom = 7'd117;			//117.33 
		6'd49:	 	sinrom = 7'd118;			//118.49 
		6'd50:	 	sinrom = 7'd120;			//119.58 
		6'd51:	 	sinrom = 7'd121;			//120.59 
		6'd52:	 	sinrom = 7'd122;			//121.53 
		6'd53:	 	sinrom = 7'd122;			//122.40 
		6'd54:	 	sinrom = 7'd123;			//123.19 
		6'd55:	 	sinrom = 7'd124;			//123.91 
		6'd56:	 	sinrom = 7'd125;			//124.56 
		6'd57:	 	sinrom = 7'd125;			//125.13 
		6'd58:	 	sinrom = 7'd126;			//125.63 
		6'd59:	 	sinrom = 7'd126;			//126.04 
		6'd60:	 	sinrom = 7'd126;			//126.39 
		6'd61:	 	sinrom = 7'd127;			//126.66 
		6'd62:	 	sinrom = 7'd127;			//126.85 
		6'd63:	 	sinrom = 7'd127;			//126.96 
	endcase 
 
endmodule