www.pudn.com > dds_quicklogic.zip > PNGEN.V

/******************************************************************************* 
  **************************************************************************** 
 **                                                                              
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 ** Project Name         : DDS                                             
 **                                                                              
 ** Author               : Daniel J. Morelli 
 ** Creation Date        : 04/10/96 20:32:05                                               
 ** Version Number       : 1.0                                                  
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 ** Revision History     :                                                       
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 ** Date          Initials         Modification                                  
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 ** Description          :                                                       
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 ** This module is a pair of GOLD code PN generators of length n=31. 
 ** These PN generators can be used to output random I and Q data to 
 ** BPSK or QPSK mmodulate the NCO.  ref Peterson and Weldon (1972). 
 **  
 **                                                                              
 *******************************************************************************/ 
 
 module pngen( 
	RESETN,				// global reset 
	PNCLK,				// PN generator clock 
	IDATA,				// I axis data 
	QDATA);				// Q axis data 
 
// Port types 
 
input PNCLK, RESETN; 
 
output IDATA, QDATA; 
 
reg[4:0] pnig1;		// I pn code generator 1 g1(p) = p^5 + p^2 + 1 
reg[4:0] pnig2;		// I pn code generator 2  
reg[4:0] pnqg1;		// Q pn code generator 1 g2(p) = p^5 + p^4 + P^2 + p + 1 
reg[4:0] pnqg2;		// Q pn code generator 2 
reg[4:0] pnig1_next;		// I pn code generator 1 g1(p) = p^5 + p^2 + 1 
reg[4:0] pnig2_next;		// I pn code generator 2  
reg[4:0] pnqg1_next;		// Q pn code generator 1 g2(p) = p^5 + p^4 + P^2 + p + 1 
reg[4:0] pnqg2_next;		// Q pn code generator 2 
 
integer lp;				// loop variable 
 
// design architecture 
	assign IDATA = pnig1[4] ^ pnig2[4]; 
	assign QDATA = pnqg1[4] ^ pnqg2[4]; 
 
	// sift register for PN code generators 
	always@(posedge PNCLK or negedge RESETN) 
	if (!RESETN) 
		begin 
			pnig1 <= 5'b10101; 
			pnqg1 <= 5'b10101; 
			pnig2 <= 5'b01101; 
			pnqg2 <= 5'b01000; 
		end 
	else 
		begin 
			pnig1 <= pnig1_next; 
			pnqg1 <= pnqg1_next; 
			pnig2 <= pnig2_next; 
			pnqg2 <= pnqg2_next; 
		end 
 
 
	always@(pnig1 or pnig2 or pnqg1 or pnqg2) 
		begin 
			pnig1_next[0] <= pnig1[4]; 
			pnig2_next[0] <= pnig2[4]; 
			pnqg1_next[0] <= pnqg1[4]; 
			pnqg2_next[0] <= pnqg2[4]; 
			for (lp = 1; lp < 5; lp = lp + 1) 
				begin 
					if (lp == 2) 
						begin 
							pnig1_next[lp] <= pnig1[lp-1] ^ pnig1[4]; 
							pnig2_next[lp] <= pnig2[lp-1] ^ pnig2[4]; 
							pnqg1_next[lp] <= pnqg1[lp-1] ^ pnqg1[4]; 
							pnqg2_next[lp] <= pnqg2[lp-1] ^ pnqg2[4]; 
						end 
					else 
						begin 
							pnig1_next[lp] <= pnig1[lp-1]; 
							pnig2_next[lp] <= pnig2[lp-1]; 
							pnqg1_next[lp] <= pnqg1[lp-1]; 
							pnqg2_next[lp] <= pnqg2[lp-1]; 
						end 
					if ((lp == 1) | (lp == 4)) 
						begin 
							pnig2_next[lp] <= pnig2[lp-1] ^ pnig2[4]; 
							pnqg2_next[lp] <= pnqg2[lp-1] ^ pnqg2[4]; 
						end 
				end 
		end 
 
endmodule