www.pudn.com > dds_quicklogic.zip > PHASEA.V

/******************************************************************************* 
**************************************************************************** 
 **                                                                              
 **                                                                              
 ** Project Name         : DDS                                             
 **                                                                              
 ** Author               : Daniel J. Morelli 
 ** Creation Date        : 03/03/96 17:59:50                                               
 ** Version Number       : 1.0                                                  
 **                                                                              
 ** Revision History     :                                                       
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 ** Date          Initials         Modification                                  
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 **                                                                              
 ** Description          :                                                       
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 ** This block is the phase accumulator of the NCO.  This block will accumulate 
 ** a 32 bit phase word with the upper 8 bits representing the actual phase  
 ** table lookup value.  This accumulator is piped in 8 bit steps.  The input to 
 ** this block is the synchronous frequency word loaded in the proper pipe order. 
 ** The output of this block is an 8 bit quantized phase value or 0 to 2pi 
 **  
 **                                                                              
 *******************************************************************************/ 
 module phasea ( 
	SYSCLK,			// system clock input 
	RESETN,			// global reset 
	SYNCFREQ,			// synchronous frequency word 
	COS,				// digital cos output 
	SIN,				// digital sin output 
	PHASE);			// 8 bit quantized phase output 
 
// Port types 
 
input SYSCLK, RESETN; 
input[31:0] SYNCFREQ; 
 
output COS,SIN; 
output[7:0] PHASE; 
 
reg[7:0] pipe1, pipe2, pipe3, pipe4;	// four levels of pipeline adders 
reg pipec1, pipec2, pipec3;				// four levels of pipeline carrys 
 
wire[7:0] add1, add2, add3, add4;		// 8 bit adders of accumulator 
wire c1, c2, c3, c4;								// carry outputs of adders 
 
supply0 gnd;									// low input 
 
// design architecture 
	assign PHASE = pipe4; 
	assign SIN = ~pipe4[7]; 
	assign COS = ~(pipe4[6] ^ pipe4[7]); 
 
  	claadd8s U_add1(pipe1, SYNCFREQ[7:0], gnd, add1, c1); 
 	claadd8s U_add2(pipe2, SYNCFREQ[15:8], pipec1, add2, c2); 
 	claadd8s U_add3(pipe3, SYNCFREQ[23:16], pipec2, add3, c3); 
 	claadd8s U_add4(pipe4, SYNCFREQ[31:24], pipec3, add4, c4); 
 
	always @(posedge SYSCLK or negedge RESETN) 
		if (!RESETN) 
		begin 
			pipe1 <= 8'h00; 
			pipe2 <= 8'h00; 
			pipe3 <= 8'h00; 
			pipe4 <= 8'h00; 
			pipec1<= 0; 
			pipec2 <= 0; 
			pipec3 <= 0; 
		end 
		else 
		begin 
			pipe1 <= add1; 
			pipe2 <= add2; 
			pipe3 <= add3; 
			pipe4 <= add4; 
			pipec1 <= c1; 
			pipec2 <= c2; 
			pipec3 <= c3; 
		end 
 
endmodule