www.pudn.com > dds_quicklogic.zip > LOADFW.V

/******************************************************************************* 
 **************************************************************************** 
 **                                                                              
 **                                                                              
 ** Project Name         : DDS                                             
 **                                                                              
 ** Author               : Daniel J. Morelli 
 ** Creation Date        : 03/03/96 21:47:34                                               
 ** Version Number       : 1.0                                                  
 **                                                                              
 ** Revision History     :                                                       
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 ** Date          Initials         Modification                                  
 **                                                                              
 **                                                                              
 ** Description          :                                                       
 **                                                                              
 ** This module will load the frequency word into the phase accumulator 
 ** synchronously at the proper pipeline timing.  The input to this module 
 ** will be the frequency word and load write strobe.  The output will be 
 ** the synchronous frequency word. 
 **  
 **                                                                              
 *******************************************************************************/ 
 
 module loadfw( 
	RESETN,				// global reset 
	SYSCLK,				// system clock 
	FREQWORD,			// input frequency word from external pins 
	FWWRN,				// low asserted frequency word write strobe 
	SYNCFREQ);			// synchronous frequency word 
 
// Port types 
 
input SYSCLK, RESETN, FWWRN; 
input[31:0] FREQWORD; 
 
output[31:0] SYNCFREQ; 
 
reg[31:0] fwreg;				// input frequency word registered 
reg fwwrnm;						// meta-stable frequency word write strobe 
reg fwwrns;						// synchronous frequency word write strobe 
reg loadp1, loadp2, loadp3, loadp4;		// pipelined load strobes 
reg[7:0] pipefw1, pipefw2, pipefw3, pipefw4;		// pipelined FW registered values 
 
// design architecture 
	assign SYNCFREQ = {pipefw4, pipefw3, pipefw2, pipefw1}; 
 
	// register the input frequency word 
	always@(posedge FWWRN or negedge RESETN) 
	if (!RESETN) 
		fwreg <= 32'h00000000; 
	else 
		fwreg <= FREQWORD; 
 
	// get a synchronous load strobe on the rising edge of FWWRN 
	always@(posedge SYSCLK or negedge RESETN) 
	if (!RESETN) 
	begin 
		fwwrnm <= 1; 
		fwwrns <= 1; 
		loadp1 <= 0; 
		loadp2 <= 0; 
		loadp3 <= 0; 
		loadp4 <= 0; 
	end 
	else 
	begin 
		fwwrnm <= FWWRN; 
		fwwrns <= fwwrnm;			// got a synchronous FRWRN 
		if ((!fwwrns)&(fwwrnm)) 
			loadp1 <= 1;				// got rising edge 
		else 
			loadp1 <= 0; 
		loadp2 <= loadp1; 
		loadp3 <= loadp2; 
		loadp4 <= loadp3; 
	end 
 
	// register the frequency word in pipeline 
	always@(posedge SYSCLK or negedge RESETN) 
	if (!RESETN) 
	begin 
		pipefw1 <= 8'h00; 
		pipefw2 <= 8'h00; 
		pipefw3 <= 8'h00; 
		pipefw4 <= 8'h00; 
	end 
	else 
	begin 
		if (loadp1) 
			pipefw1 <= fwreg[7:0]; 
		else 
			pipefw1 <= pipefw1; 
		if (loadp2) 
			pipefw2 <= fwreg[15:8]; 
		else 
			pipefw2 <= pipefw2; 
		if (loadp3) 
			pipefw3 <= fwreg[23:16]; 
		else 
			pipefw3 <= pipefw3; 
		if (loadp4) 
			pipefw4 <= fwreg[31:24]; 
		else 
			pipefw4 <= pipefw4; 
	end 
 
endmodule