www.pudn.com > dds_quicklogic.zip > DDS.V

`include "romtab.v" 
`include "claadd8s.v" 
`include "loadfw.v" 
`include "loadpw.v" 
`include "sinlup.v" 
`include "phasea.v" 
`include "phasemod.v" 
`include "pngen.v" 
 
/******************************************************************************* 
 **************************************************************************** 
 **                                                                              
 **                                                                              
 ** Project Name         : DDS                                             
 **                                                                              
 ** Author               : Daniel J. Morelli 
 ** Creation Date        : 03/04/96 21:51:00                                               
 ** Version Number       : 1.0                                                  
 **                                                                              
 ** Revision History     :                                                       
 **                                                                              
 ** Date          Initials         Modification                                  
 **                                                                              
 **                                                                              
 ** Description          :                                                       
 **                                                                              
 ** This is the top level of the Direct Digital Synthesizer 
 **  
 **                                                                              
 *******************************************************************************/ 
 
 module dds( 
	RESETN,				// global reset 
	PNCLK,				// PN generator clock 
	SYSCLK,				// system clock 
	FREQWORD,			// input frequency word from external pins 
	FWWRN,				// low asserted frequency word write strobe 
	PHASEWORD,			// input phase word from external pins 
	PWWRN,				// low asserted frequency word write strobe 
	IDATA,				// I axis data 
	QDATA,				// Q axis data 
	COS,					// digital cos output 
	SIN,					// digital sin output 
	MCOS,					// modulated digital cos output 
	MSIN,					// modulated digital sin output 
	DACCLK,				// DAC clock to signal when to load DDS sin value 
	DACOUT);				// DAC output of sin wave 
 
// Port types 
 
input SYSCLK, PNCLK, RESETN, FWWRN, PWWRN; 
input[31:0] FREQWORD; 
input[7:0] PHASEWORD; 
 
output DACCLK, COS, SIN, MCOS, MSIN, IDATA, QDATA; 
output[7:0] DACOUT; 
 
wire[31:0] 	syncfreq;		//synchronous frequency word 
wire[7:0]	syncphswd;		//synchronous phase word 
wire[7:0] 	phase;			// phase output from phase accumulator 
wire[7:0]	modphase;		// modulated phase value after phase mod block 
 
// design architecture 
	assign DACCLK = SYSCLK; 
 
//--------------------------------------------------------------- 
// this module is not part of the NCO 
// this module is used to generate random data 
// to modulate the NCO output 
//--------------------------------------------------------------- 
 pngen U_pngen( 
	RESETN,				// global reset 
	PNCLK,				// PN generator clock 
	IDATA,				// I axis data 
	QDATA);				// Q axis data 
//--------------------------------------------------------------- 
 
 loadfw U_loadfw( 
	RESETN,			// global reset 
	SYSCLK,			// system clock 
	FREQWORD,		// input frequency word from external pins 
	FWWRN,			// low asserted frequency word write strobe 
	syncfreq);		// synchronous frequency word 
 
 loadpw U_loadpw( 
	RESETN,			// global reset 
	SYSCLK,			// system clock 
	PHASEWORD,		// input phase word from external pins 
	PWWRN,			// low asserted frequency word write strobe 
	syncphswd);		// synchronous phase word 
 
 phasea U_phasea( 
	SYSCLK,			// system clock input 
	RESETN,			// global reset 
	syncfreq,		// synchronous frequency word 
	COS,				// digital cos output 
	SIN,				// digital sin output 
	phase);			// 8 bit quantized phase output 
 
 phasemod U_phasemod ( 
	SYSCLK,			// system clock input 
	RESETN,			// global reset 
	syncphswd,		// synchronous phase word 
	phase,			// 8 bit quantized phase value 
	MCOS,				// modulated digital cos output 
	MSIN,				// modulated digital sin output 
	modphase);		// modulated phase output 
 
 sinlup U_sinlup ( 
	SYSCLK,			// system clock input 
	RESETN,			// global reset 
	modphase,		// modulated phase output 
	DACOUT);			// DAC output of sin wave 
 
endmodule