www.pudn.com > vXworksBSPfors3c44b0.rar > target.nr
'\" t
.so wrs.an
.\" wrSbcArm7/target.nr - SBCARM7 target specific documentation
.\"
.\" Copyright 1984-2000 Wind River Systems, Inc.
.\"
.\" modification history
.\" --------------------
.\" 02a,27aug01,dgp change manual pages to reference entries per SPR 23698
.\" 01a,11apr01,g_l baseline version
.\"
.\"
.TH wrSbcArm7 T "Wind River SBCARM7 single board computer, ARM7tdmi" "Rev: 10 Oct 01" "TORNADO REFERENCE: VXWORKS"
.SH "NAME"
.aX "Wind River SBCARM7 single board computer, ARM7tdmi"
.SH "INTRODUCTION"
This reference entry provides board-specific information necessary to run
VxWorks for the wrSbcArm7 BSP. Before running VxWorks, verify that the
board runs in the factory configuration using the Wind River visionWARE supplied
on the board flash.
.SS "Samsung S3C4510X01 Device"
This BSP is designed around the capabilities of the S3C4510X01 Samsung chip.
Note that there is an inconsistency in the Samsung part numbering scheme.
Some documents refer to this Samsung chip as part number KS32C50100. This
document refers to the chip as the S3C4510X01 which is the current part
number for this device. Both numbers refer to the same device.
.SS "Little-Endian Byte Order"
If the BSP is to be used in little-endian byte order mode, set the
'Configuration' DIP switch 'S5-6' to the 'closed' position. Boot ROM
and VxWorks images built from either of the following directories may
be used: 'wrSbcArm7' or 'wrSbcArm7_t'. Make sure the switch is
'fully' in its closed position.
For correct operation, both the boot ROM image, which resides in
flash, and the VxWorks image, which is downloaded, must be compiled for
little-endian mode.
.SS "Big-Endian Byte Order"
If the BSP is to be used in big-endian byte order mode, set the
'Configuration' DIP switch 'S5-6' to the 'open' position. Boot ROM
and VxWorks images built from either of the following directories may
be used: 'wrSbcArm7_be' or 'wrSbcArm7_tbe'. Make sure the switch is
'fully' in its closed position.
For correct operation, both the boot ROM image, which resides in flash,
and the VxWorks image, which is downloaded, must be compiled for
big-endian mode.
If the board is booted in big-endian mode, a '(BE)' is displayed on
the LCD screen.
.SS "Thumb mode"
No special DIP-switch settings are necessary to use this BSP in 16-bit
thumb mode. Boot ROM and VxWorks images built from either of the
following directories run the CPU in thumb mode: 'wrSbcArm7_t' or
'wrSbcArm7_tbe'. The other two wrSbcArm7 related directories
operate the CPU in the more commonly used 32-bit ARM mode.
Although the operating system appears to function correctly when the
boot ROM thumb/ARM mode does not match the VxWorks thumb/ARM mode, this
configuration has not been thoroughly tested and is not supported by
Wind River. It is recommended that if VxWorks is built in thumb
mode, then the boot ROM in flash should also be built in thumb mode.
Similarly, if one image is built in ARM mode, the other image
should also be built in ARM mode.
If the board is booted with a thumb image, lower case '(t)' is
displayed on the LCD screen. If the board is running in big-endian
and thumb mode then the label is '(tBE)'.
.SS "BOOT ROMS"
The boot ROM images, 'bootrom_uncmp.bin' and 'bootrom.bin', are provided
with this BSP. The boot ROM is configured to be placed in memory at a ROM
base address of 0x0. This BSP is configured to work in little-endian mode
and to use the 2 MB on-board flash ROM, the Samsung S3C4510X01 100\10BaseT
Ethernet as the default boot device, and the Samsung S3C4510X01 UART as
the console device.
.SS "Programming the Boot ROM Images to the SBCARM7 Flash"
To program the boot ROMs, first install the visionPROBE II or visionICE II
and power it on. Connect the visionPROBE II or visionICE II JTAG interface
cable to the SBCARM7 board JTAG connector (JP2, the JTAG port) at the top
edge of the board next to the LCD display.
Once all of the connections have been made, power up the SBCARM7 board
and start the visionCLICK executable on the host.
.IP "Configuring the visionCLICK Project"
At this point, the 'Welcome To visionCLICK' window appears. In this
window, click the 'Configure' button, this invokes the 'PROJECTS/LOAD'
window. In this window, click the '+' left to
'ARM7TDMI_C_Demo_LE_GNU_0x01000000.prj', this shows the project
configuration. Use the mouse to select the 'Microprocessors' option and
right-click, select the following type of CPU: 'ARM->ARM7->ARM7TDMI'. Now
verify that the 'Target Control' option points to 'visionPROBE' for
visionPROBE I/II or 'visionICE' for visionICE I/II. Also, select the
'Communications' tab and verify that the 'Normal Port/Rate' and
'Download Port/Rate' settings are correct for your connection, for example:
'LPT1' for visionPROBE II. Now click the 'Save' button at the bottom of
the window and then click the 'Activate' button.
.IP "Programming visionPROBE II / visionICE II with the Proper Register Setting"
Go to the 'Tools' menu and select the 'Log Output/Playback Scripts' option,
the 'Record / Playback' dialog box appears. In this dialog box, go to the
'Playback Commands From File' group and click the 'Browse' button.
Navigate to the location of the register file that matches your board, for
example: 'samsungKS32c_RamAt0.reg' for the SBCARM7 board with the Samsung
S3C4510X01 50Mhz. After choosing the register file, click the 'Open'
button to confirm the selected register file. This returns you to the
'Record / Playback' dialog box. Now click the 'Start' button located in
the same group. In the 'Terminal' window, visionCLICK is running the
script. When visionCLICK finishes the playback, the '>BKM>' or the '>ERR>'
prompt will appear.
Note that you should select a proper register file that correctly
represents the endian byte order of the board switch settings.
Usually, the endian is configured in the first few lines of the
register file. If your board is little-endian byte order, the
configuration line must read:
.CS
"CF LENDIAN YES"
.CE
If your board is big-endian byte order, the configuration line must be
set to the following:
.CS
"CF LENDIAN NO"
.CE
.IP "Getting into Background Mode"
Execute the 'IN' command to reset the board and initialize it with the
register setting.
.LP
.CS
IN
.CE
.IP " "
This command is the reset command to initialize the board. After you get
the '>BKM>' prompt continue with the instructions in the next section.
.IP "Converting 'bootrom' or 'bootrom_uncmp' and other rom images"
To convert 'bootrom' or 'bootrom_uncmp' to 'bootrom.bin' or
'bootrom_uncmp.bin', complete the following steps:
1)
In the 'Tools' menu, choose 'Convert Object Modules'.
2)
The 'CONVERT BINARY AND SYMBOL OBJs' dialog appears.
Specify the file to convert by browsing for or typing in the path to a
file in the field labeled 'Select Input Object Module To Convert'.
For example, you might enter 'd:\tornado\target\config\wrSbcArm7\bootrom'.
Check the 'Create Flat BIN File For Flash Programming' box only
(unless you also want to create debug files as well).
In the field labeled 'In Range Of 0x', enter one of the following numbers:
.TS
expand;
1 1 .
File | Number
_
'bootrom' | 6000
'bootrom_uncmp' | 480000
'vxWorks.res_rom' | 1000000
.TE
In the 'To 0x' edit box, enter a large enough number such as the following:
.TS
expand;
1 1 .
File | Number
_
'bootrom' | FFFFFFFF
'bootrom_uncmp' | FFFFFFFF
'vxWorks.res_rom' | FFFFFFFF
.TE
Note that the user may choose to check multiple boxes at the same
time to generate multiple output file types. The symbol file
and RAM download files are useful for debugging scenarios not
discussed in this example covering flash download.
3)
In the 'Miscellaneous Parameters' edit box, enter the following extra
parameters:
.LP
.CS
-w -t arm -g
.CE
.IP " "
Make sure you have at least one space between each parameter.
4)
After configuring the 'convert' dialog box, click the 'Convert' button.
A DOS window appears and asks you to press any key. Pressing any key
will close this window and finish the convert utility work.
Do not click the 'OK' button until after you have converted the image.
The 'OK' button simply closes the dialog box.
5)
Now click the 'OK' button to close the dialog box and continue with the
next step, 'Programming the SBCARM7 Flash'.
.LP
.IP "Programming the SBCARM7 Flash"
In visionCLICK, select 'Program Flash Devices' from the Tools pull-down
menu, this invokes the 'TF FLASH PROGRAMMING' window. If you are not using
visionCLICK, you can also invoke this window using the
'visionICE Utilities Panel'. Complete the following steps:
1)
In the 'Flash Card or PC Host File Name and Path' group, enter the full
path to the location of the 'bootrom_uncmp.bin' or the 'bootrom.bin' file
in the edit box. You can also use the 'Select' button to browse for the
file location.
2)
In the 'Flash Card or PC Host File Name and Path' group, click the
'Select' button. The 'CHOOSE A FILE FROM HOST PC' dialog box appears. Go
to the '+/- Bias' group and enter the number that corresponds to your
boot ROM file:
.TS
expand;
1 1 .
File | Number
_
'bootrom.bin' | -6000
'bootrom_uncmp.bin' | -480000
'vxWorks.bin (res_rom)' | -1000000
or
'bootrom.bin' | FFA000
'bootrom_uncmp.bin' | B80000
'vxWorks.bin (res_rom)' | 0
.TE
Click the 'OK' button to continue.
The negative numbers above assume flash has been initialized to 0x0.
The positive numbers assume flash has been initialized to 0x1000000.
This forces the image that was built to start at 0x6000 or 0x480000 to be
programmed at the beginning of flash (that is, 0x6000-0x6000=0x0 or
0x6000+FFA000=0x1000000).
If you are unsure about where flash begins, reset the target, then try
to write to memory at either 0x0 or 0x1000000 using the visionProbe
connected to the visionClick debugger. If the write fails, this is
probably the initialized location of flash. If you do not reset the
target before doing this and cache is enabled, you may be able to
modify a FLASH address temporarily if it has been cached.
3)
In the 'Programming Algorithm' group, click the 'Select' button and select
the following flash device:
For the 2 MB on-board flash : 'AMD 29F800T ( 512 x 16 ) 2 Devices'
4)
Set the proper address of the flash to 0 (or 01000000) and check
the 'Erase to 0x' radio button. Set the upper limit of flash to 6ffff
(or 106ffff). Set the 'Available RAM Workspace Start Address' setting
to 01000000 (or 00000000) and the 'Bytes Of Target RAM Required' to
around 60000 (this precise number is not important here).
Note: limiting the region of flash to be erased ensures that NVRAM is
not erased. If the 'Erase All' button is pressed, then NVRAM will be
erased.
The 'RAM Workspace' is scratch memory in RAM used by the visionPROBE flash
programming algorithm.
5)
Click the 'Erase and Program' button.
.LP
.IP "Running the VxWorks Boot ROM Program"
At this point, the on-board local flash memory is programmed with the new
boot program. To execute this new boot program, turn the board off and on,
possibly disconnecting the visionPROBE in the process. If the
visionPROBE I/II or the visionICE I/II is still connected to the board,
the processor is stopped at the first instruction to execute. If either the
visionICE or the JTAG probe are not connected, the boot ROM image will execute
and prompt the user via the serial port to download a VxWorks image.
.LP
To load VxWorks, and for more information, follow the instructions in the
.pG "Getting Started".
An alternative way to load vxWorks is through vWARE.
.SS "Using visionWARE to run VxWorks"
The following section explains how to launch VxWorks using visionWARE as a boot loader.
Complete the following steps:
1. Connect your SBCARM7 serial channel (COM1) to a host running a
terminal program at 9600 baud (for example, '
HyperTerminal') using the supplied serial cable.
2. Connect your SBCARM7 100\10Base-T RJ45 connector (JP13) port to
a network hub.
3. Open a TFTP server and point to the location of the 'vxWorks.bdx'
file. If you want to use the TFTP server that is supplied with
visionWARE, go to the visionWARE directory on your host and
locate the 'tftp' directory in the visionWARE root directory.
The 'tftp' directory contains an application called 'tftpd32.exe'.
This application launches the TFTPD32 window. In the TFTPD32
window, click the 'Settings' button. This invokes
'Tftpd32: Settings'. Go to the 'Base Directory' group and
type the full path to your VxWorks image inside the edit box,
or use the 'Browse' button to navigate to your image.
4. Power up your SBCARM7 and, from the serial terminal, press
any key within 1 second to abort the boot script. This displays
a '>BKM>' prompt.
5. Type the 'shell' command and press enter. The following line
appears: 'Boot Delay (seconds) = 6 >' . Specify the desired
delay value and press enter.
6. The next line is: ' Boot Script = >' . Type the boot script
command. For example, if your host computer was named
'BOS-GILH', you would type the following:
"load \\\\BOS-GILH\vxWorks.bdx!launch 6000"
and then press enter.
Note(s):
** It is very important to keep the same space between the
'load' command and the host name '\\\\BOS-GILH'.
** It is also very important to keep the same space between
the 'launch' command and the '6000'.
** The host name should be the same as specified in the
"Remote System 1 Name" line.
7. The next line is "MAC Address = 00-A0-1E-08-04-9A >" . If you
want to change the target MAC address, type it now and press
enter, else just press enter.
8. The next line is "IP Address = 0.0.0.0 >" . Type your target
IP address. For example: 24.42.124.92, and press enter.
9. The next line is "Subnet Mask = 0.0.0.0 >" . If you want to
use a subnet mask, type it now and press enter, else just press
enter.
10. The next line is "Default Gateway = 0.0.0.0 >" . If you want
to use a default gateway, type it now and press enter, else just
press enter.
11. The next line is "Remote System 1 Name = >" . Type the same
host name you specified in the 'Boot Script' line.
12. The next line is "Remote System 1 IP = >" . Type your host
IP address. For example: 24.42.124.94 and press enter.
13. Press enter after each of the following lines:
"Remote System 2 Name = >"
"Remote System 3 Name = >"
"Remote System 4 Name = >"
14. The following message appears:
Saving changes will generate a reboot.
Save Changes (y/n)?
Press 'y' to save the changes.
The changes are now saved. The board will restart visionWARE and
boot VxWorks. After a few seconds, the following messages appear:
.CS
Wind River visionWARE v2.00 EAR for SBC-ARM50100
Wind River HSI +1(781) 828 5588
Build #6, 04/17/01 16:16:56
MAC : 00-A0-1E-08-04-9A IP : 24.42.124.92
Type "shell" to set IP and/or MAC addresses
Type "help" to see available commands
Press a key in the next <6> seconds to preempt boot script
Booting from script...
load \\BOS-GILH\vxWorks.bdx!launch 6000
>RUN>‘Attached TCP/IP interface to sng unit 0
Attaching interface lo0...done
VxWorks
Copyright 1984-2001 Wind River Systems, Inc.
CPU: KS32C50100 for WindRiver SBC ARM7
VxWorks: 5.4.1
BSP version: 1.2/13
Creation date: Jul 23 2001
WDB: Ready.
.CE
For more information regarding visionWARE boot services and the visionWARE development kit,
please refer to the visionWARE manuals located on the CD-ROM shipped with your board.
.SH "BOOT DEVICES"
The only supported boot device is:
.TS
expand;
1 1 .
'sng' | 100\10BaseT Ethernet (in the Samsung CPU ASIC)
.TE
.SS "Jumpers and Switches"
No jumpers are relevant to VxWorks configuration. However, to
get the board running with the default configuration, the following
jumpers and switches must be set as follows:
.TS
expand;
1 1 .
Jumper Settings
_
JP4 | Close
JP5 | 1-2, 3-4, 5-6, 7-8
JP11 | All Open
JP12 | 5-6, 9-10
JP14 | 1-3, 2-4
JP16 | 1-3, 2-4
JP17 | 1-3, 2-4
JP23 | 1-2, 3-4, 5-6
JP24 | 1-2, 3-4, 5-6
|
** NOTE: | If the jumper contains more then two pins the pin numbers
| that are open will not by specified here, only the pin
| numbers that are closed (connected) are specified.
.TE
.TS
expand;
1 1 1 1 1 1 1 1 1 .
Switch Settings
-
| S4-1 Open | | S3-1 Close | | S5-1 Close | | SW3-1 On
| S4-2 Open | | S3-2 Close | | S5-2 Open | | SW3-2 Off
| S4-3 Open | | S3-3 Close | | S5-3 Open | | SW3-3 Off
| S4-4 Open | | S3-4 Close | | S5-4 Open | | SW3-4 Off
| S4-5 Open | | S3-5 Close | | S5-5 Open | | SW3-5 Off
| S4-6 Open | | S3-6 Open | | S5-6 Close | | SW3-6 On
| S4-7 Open | | S3-7 Close | | S5-7 Close
| S4-8 Open | | S3-8 Close | | S5-8 Close
.TE
.SH "FEATURES"
This section describes the supported and unsupported features of the SBCARM7
.SS "Supported Features"
The supported features of the SBCARM7 board include:
- Samsung's KS32C50100 microprocessor (based on an ARM7TDMI Core)
- Little-Endian or Big-Endian byte order
- ARM or Thumb mode
- Board Initialization
- The two KS32C50100 32-bit timers used to implement a System clock,
Aux clock, and Timestamp clock.
- The first KS32C50100 UART channel for COM1 (Console channel).
- The KS32C50100 Ethernet controller as an Ethernet device
supporting 100\10BaseT protocol.
- The KS32C50100 Interrupt Controller.
- 8 MB on-board DRAM.
- 2 MB on-board flash.
- 50 MHz CPU speeds.
- Cache support.
- Emulating NvRam on flash.
.SS "Unsupported Features"
The items not supported on the SBCARM7 board are:
- IIC support.
- HDLC support.
- CAN Bus support.
.SH "HARDWARE DETAILS"
This section documents the details of the device drivers and board
hardware elements for the SBCARM7.
.SS "Devices"
The device drivers included are:
.TS
expand;
1 1 .
Device Drivers
_
sngks32cTimer.c | SNGKS32CARM7 timer driver
sngks32cIntrCtl.c | SNGKS32CARM7 interrupt controller driver
sngks32cSio.c | SNGKS32CARM7 serial driver
'sngks32cEnd.o' | SNGKS32CARM7 Ethernet driver
sysSerial.c | serial device initialization routines
sysEnd.c | END network driver support routines
sysLcd.c | SBCARM7 LCD driver
sysLed.c | SBCARM7 User LED driver
nullNvRam.c | dummy non-volatile RAM library
.TE
The timer driver, 'sngks32cTimer', implements a system clock,
auxiliary clock, and timestamp clock using the two SNGKS32CARM7 32-bit
timers. This BSP configures the SNGKS32CARM7 first UART to implement a
console device and the SNGKS32CARM7 Ethernet controller to implement
an Ethernet port.
.SS "Default Memory Map"
The following is the memory map from the CPU point of view (before RAM and
ROM are swapped in 'romInit' early during boot ROM execution).
.TS
expand;
1 1 1 1 1 .
Chip | Select | Start | Size | Access to
_
nRCS0 | R/W | 0x0 | 2 MB | External flash Boot ROM
nRCS2 | R/W | 0x03FB0000 | 8 KB | External EEPROM
nRCS3 | R/W | 0x03FC0000 | 64 KB | External Register (MailBox)
nRDCS0 | R/W | 0x01000000 | 16 MB | External SDRAM
nECS1 | R | 0x03FD4000 | 256 Byte | External Register (8 Switch Bank)
nECS1 | W | 0x03FD4000 | 256 Byte | External Register (8 LED Bank)
nECS1 | R | 0x03FD4100 | 16 KB | External Display (LCD)
nECS2 | R/W | 0x03FD8000 | 16 KB | External CAN 1 controller
nECS3 | R/W | 0x03FDC000 | 16 KB | External CAN 2 controller
' ' | R/W | 0x03FE0000 | 8 KB | Internal SRAM
' ' | R/W | 0x03FF0000 | 24 KB | Internal Registers
.TE
.SS "Shared Memory"
Does not apply.
.SS "Interrupts"
21 interrupt levels are provided:
.TS
expand;
1 1 .
Interrupt Levels
_
0 | External Interrupt 0
1 | External Interrupt 1
2 | External Interrupt 2
3 | External Interrupt 3
4 | UART 0 Transmit Interrupt
5 | UART 0 Receive and Error Interrupt
6 | UART 1 Transmit Interrupt
7 | UART 1 Receive and Error Interrupt
8 | GDMA channel 0 interrupt
9 | GDMA channel 1 interrupt
10 | Timer 0 Interrupt
11 | Timer 1 Interrupt
12 | HDLC channel A Tx interrupt
13 | HDLC channel A Rx interrupt
14 | HDLC channel B Tx interrupt
15 | HDLC channel B Rx interrupt
16 | Ethernet controller BDMA Tx Interrupt
17 | Ethernet controller BDMA Rx Interrupt
18 | Ethernet controller MAC Tx Interrupt
19 | Ethernet controller MAC Rx Interrupt
20 | IIC -Bus Interrupt
.TE
.SS "Ethernet Port"
The BSP configures itself to use the KS32C50100 Ethernet Controller as its
Ethernet port. The name `sng' should be specified as the boot device
to the boot ROMs when booting VxWorks via Ethernet. This BSP is
configured to use an END-style network driver.
.SS " NVRAM Support"
The booting parameters (otherwise known as the boot line) are automatically
saved in NVRAM after the user configures startup information the first
time the boot ROM is executed. This allows unattended booting during
future power off/on cycles.
.SS "Changing the Ethernet Address"
The SBCARM7 boards do not have unique Ethernet hardware addresses. If
the boards are to be connected to a network, unique hardware addresses
must be provided. Thus, the user must provide a suitable 6-byte
Ethernet address for each board used on a network. If the board uses
a 'bootrom' type image and not 'visionWare' image to boot, the default
Ethernet address is specified in the 'wrSbcArm7.h' file in the
following line:
.CS
#define ETHERNET_MAC_ADRS { 0x00, 0xA0, 0x88, 0x88, 0x88, 0x00 }
.CE
This address is modified during initialization by DIP-switch settings
on the 'user switches', 'S4'. The least significant byte (the 6th byte
using network order) takes on the 8-bit value of 'S4' where any 'open'
position becomes a binary '0' and any 'closed' position becomes a
binary '1'.
To change any other byte of the MAC address, the ETHERNET_MAC_ADRS
macro must be modified, a new boot ROM must be built and burned into
flash, and a new VxWorks image must be built.
Check with your system administrator to ensure that you have a unique
MAC address for your site.
.SS "CPU Speed"
Two types of clock inputs are used on the board. The first, main
clock, is a 50 MHz 1:1 Oscillator plugged into the UX1 socket to drive
the CPU clock at 50 MHz. The second is a 16 MHz 1:1 Oscillator used for
the HDLC channel that is plugged into the UX4 socket. By default the
UX3 and UX2 sockets are empty. These sockets are used for the CAN bus
Oscillator.
.SS "Serial Configuration"
SMC1 is configured as a UART device with 8 data bits, 1 stop bit,
hardware handshaking, and parity disabled.
.SS "Serial Connections"
COM1 and COM2 may be connected via a simple 3 wire connection using
standard phone jacks.
pin 1 = RIN
pin 2 = TOUT
pin 3 = NC
pin 4 = GND
Alternatively, COM1 may be connected through a standard male DB9
connector.
.SS "Network Configuration"
The Ethernet is configured as a 100\10 Mb/s Ethernet port
.SS "ROM Considerations"
Go to the 'Build' menu in Tornado II and choose 'Build Boot Rom...'.
In the dialog box, choose 'wrSbcArm7' on the left side and 'bootrom' on
the right side. Use the visionPROBE II or visionICE II to convert the
'bootrom' image to a 'bootrom.bin' image and to program the flash. Make
sure the file is loaded into flash at the starting address 0x0.
.SS "Delivered Objects"
Does not apply.
.SS "Make Targets"
Only 'bootrom_uncmp', 'bootrom', and 'vxWorks' have been tested.
.SS "Unix Distribution"
At the current time, Wind River only supplies a PC version of this BSP.
.SH "SPECIAL CONSIDERATIONS"
This section describes miscellaneous information about this BSP.
.SS "Known Problems"
The following items are known problems for this release:
.IP " "
There appears to be a hardware bug in the Samsung KS32C50100. The
instruction 'LDR rx, [ry]' will cause a 'data abort' to occur when
'ry' is not aligned on a word boundary. According to the
specifications, neither a 'data abort', nor any other exception, should occur
if the memory referenced by 'ry' is in a legal range, regardless of
alignment.
.LP
.IP " "
As a consequence of this bug, the standard checksum function used in
other ARMARCH4 processors will fail. The file sbcCksum.c is provided
in the 'wrSbcArm7' BSP directory as a workaround to this problem.
.LP
.SH "BOARD LAYOUT"
The diagrams below show the relevant jumpers for VxWorks configuration.
Note: When changing any DIP switches, make sure the switch is left
fully in the 'on' position or in the 'off' position. If a switch is
left at an intermediate state, the results are unpredictable.
.bS
____ ____
_|JP25|_|JP26|______________________________________________________________
| |____| |____| |JP3 | |JP2 | | |
--- ---- ---- | |
| | --- ___ | LCD |
| | |SW2| | | | |
|P1 | --- | | | |
| | ________ |96 | |______________________________________________|
| | |||||||||D5 | | __ ___________ |
|___| -------- |PIN| | || J3 | |
| -------- | | |J2||___________| -- JP4 |
| | S4 | |DIN| | | ___________ ___ ___|
--- -------- | | | || ARM| |UX1| |JP |
| | ___ ___ |Exp| |__||SAMSUNG | |___| |22 |
| | |SW3| |UX3| | | __ |S3C4510X01 | ___________ |___|
|P2 | |___| |___| | | | || | | S3 | |
| | ___ |JP | |J4||___________| |___________| |
| | |UX4| |18 | | | _ ___________ ___|
|___| |___| |___| | |JP17 JP14|S|| S5 | | |
| ___ |__|||| ||| ||| |W||___________| |JP1|
| |UX2| JP16 |1| |___|
--- |___| |_| |
| | Wind River H.S.I |
|COM| JP12 SBC ARM7 |
| 1 | ||||| JP5 |
|___| JP11 JP23 JP24 |||| |
| ||||| |||| |||| __ |
| ____ ____ ____ ____ ____ S2 __ __ __ | | |
|____|COM1|__|COM2|____|CAN1|_|CAN2|__|Ethe|_____||_|D4|_|D3|_|D2|_|S1|______|
|____| |____| |____| |____| |____| || |__| |__| |__| |__|
.bE
Key:
.TS
expand;
1 1 .
SW1 - Ethernet Configuration Switch Box
_
SW1-1 | TXSLEW0
SW1-2 | TXSLEW1
SW1-3 | The LXT972 advertises pause capabilities.
SW1-4 | The LXT972 is in PWRDWN mode.
SW1-5 | The MDIO is disabled.
SW1-6 | ON Sets the device address (ON=LOW), (OFF=HIGH)
.TE
.TS
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1 1 .
SW2 - RS232 / RS485 Select
_
SW2-1 | HDLC Port A, When on, the nRTSA controls the RS485 transmit enable.
SW2-2 | HDLC Port A, When on, the CPU port pin P5 controls the RS485 transmit enable.
SW2-3 | HDLC Port B, When on, the nRTSB controls the RS485 transmit enable
SW2-4 | HDLC Port B, When on, the CPU Port pin P6 controls the RS485 transmit enable.
SW2-5 | HDLC Port A, Signal SELA ON for the RS232 drivers and OFF for the RS485 drivers.
SW2-6 | HDLC Port B, Signal SELB ON for the RS232 drivers and OFF for the RS485 drivers.
.TE
.TS
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1 1 .
SW3 - Switch Descriptions
_
SW3-1 | When on, the incoming receive clock is used as HDLC Port A (RXCA)
SW3-2 | When on, the external oscillator UX3 is used as RXCA
SW3-3 | When on, the external oscillator UX3 is used as a transmit clock on
| HDLC Port A (TXCA)
SW3-4 | When on, the external oscillator UX3 is used as the receive clock on
| HDLC Port B (RXCB)
SW3-5 | When on, external oscillator UX3 is used as a transmit clock on HDLC
| Port B (TXCB)
SW3-6 | When on, the incoming receive clock is used as HDLC Port B (RXCB).
.TE
.TS
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1 1 .
S3 - Chip Select Isolation Switch Box
_
S3-1 | nECS1 User I/O, 8 Switch Bank, 8 LEDs, LCD Display
S3-2 | nECS2 CAN 1 Controller IC
S3-3 | nECS3 CAN2 Controller IC
S3-4 | nRCS1 Mailbox Connector
S3-5 | nRCS0 2 MB Boot Flash
S3-6 | nRCS0 16 MB Boot Flash
S3-7 | nRCS2 8 Kb x 8 EEPROM
S3-8 | nRAS0 16 MB SDRAM (nSDRAM_CS)
.TE
.TS
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S4 - User Switches
_
The user switches are used to set a unique MAC address.
.TE
.TS
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1 1 .
S5 - CPU Configuration Switch Box
_
S5-1 | TMODE/PLL MF. The functionality depends on the position of the CLKSEL switch.
| If the CLKSEL Switch is CLOSED then CLOSED=Normal operating mode and OPEN=Test
| Mode. But if the CLKSEL Switch is CLOSED then CLOSED = PLL MF OF 5 (5x), and
| OPEN=PLL MF 0F 6.6(6.6X).
S5-2 | nP4RESET OPEN When enabled, a low on CPU Port bit P4 will
| reset both CAN interfaces and the ethernet chip.
S5-3 | EN_nTRST When CLOSED, a power on reset will issue a JTAG TRST.
S5-4 | BOSIZE0
S5-5 | BOSIZE1
S5-6 | LITTLE When set to CLOSED, Little-endian is enabled. When set to OPEN,
| Big-endian is enabled.
.TE
.TS
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1 1 .
Other Connections
_
P1 | HDLC Ports A (RS232 Drivers)
P2 | HDLC Ports B (RS232 Drivers)
S1 | Power/Reset switch
S2 | Interrupt 0 switch
D2 | Power LED
D3-4 | D3 and D4 are amber LEDs that reflect what is on port bits 0 and 1,
| two general purpose I/O pins on the processor. If you write a 0 to
| either of these pins, the LEDs will turn on.
D5 | User LED's
J2 | Mictor Connectors
J3 | Mictor Connectors
J4 | Mictor Connectors
JP1 | +5V/+12 Power
JP2 | 14-Pin JTAG Debug Interface
JP3 | Wind River Mailbox Connector
JP4 | CHN_JTAG
JP11 | 10-Pin IDE Connector on UART1
JP12 | IRDA
JP14 | Ethernet LED Configuration Bits LED/CFG1
JP16 | Ethernet LED Configuration Bits LED/CFG2
JP17 | Ethernet LED Configuration Bits LED/CFG3
JP18 | 96-Pin DIN Expansion Connector
JP22 | +5V/+12V Power
JP23 | CAN1 Interfaces - Jumper Options
JP24 | CAN2 Interfaces - Jumper Options
JP25 | HDLC Ports A (RS485 Drivers)
JP26 | HDLC Ports B (RS485 Drivers)
UX1 | CPU Oscillator
UX2 | CAN Oscillator
UX3 | CAN Oscillator
UX4 | HDLC Oscillator
.TE
.SH SEE ALSO
.tG "Getting Started,"
.pG "Configuration."
.SH "BIBLIOGRAPHY"
.iB "Wind River HSI ARM7 Reference Design"
.iB "Advanced RISC Machines, ARM 7TDMI Data Sheet"
.iB "Samsung KS32C50100 User's Manual"
.iB "Samsung KS32C50100/5000A Application Notes"