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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity shift_3 is

port(clk,resetn,d_in:in std_logic;
     shift_en:in std_logic;
     shift_out0:out std_logic;
     shift_out1:out std_logic;
     shift_out2:out std_logic);
end shift_3;

architecture shift_3 of shift_3 is
    signal shift_reg:std_logic_vector(2 downto 0);
    signal shift_enm:std_logic;
begin
  process(clk,resetn)
  begin
            if resetn='0'then
                shift_reg<=(others=>'0');
                shift_enm<='0';
elsif clk'event and clk='1' then
    shift_enm<=shift_en;
        if shift_enm='1' then
shift_reg<=std_logic_vector(shl(unsigned(shift_reg),"1"));
end if;
shift_reg(0)<=d_in;
        end if;
end process;
shift_out0<=shift_reg(0);
shift_out1<=shift_reg(1);
shift_out2<=shift_reg(2);
end shift_3;