www.pudn.com > equlizer.rar > s_term3.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE work.equ_pak.all;

ENTITY p_s1 IS
PORT(clk: in std_logic;
resetn: in std_logic:='1';
load_n:in std_logic:='0';
shift_en: in std_logic:='0';
parallel_in : in std_logic_vector(1 downto 0);
serial_out: out std_logic;
addr_st: out std_logic);
END p_s1;

ARCHITECTURE rt1 OF p_s1 IS
SIGNAL load_nm, shift_enm:std_logic;
BEGIN
PROCESS(clk,resetn)
BEGIN
IF resetn='0' then
serial_out<='0';
addr_st<='0';
load_nm<='0';
shift_enm<='0';
ELSIF clk'event and clk='1' then
load_nm<=load_n;
shift_enm<=shift_en;
If load_nm='1' then
serial_out<=parallel_in(0);
addr_st<='1';
ELSIF shift_enm='1' then
serial_out<=parallel_in(1);
addr_st<='1';
ELSE
serial_out<='0';
addr_st<='0';
END IF;
END IF;
END PROCESS;
END rt1;

LIBRARY ieee;
use ieee.std_logic_1164.all;
USE work.equ_pak.all;

ENTITY s_term3 IS
GENERIC(n: positive:=3);
PORT(clk: in std_logic;
resetn: in std_logic:='1';
load:in std_logic:='0';
shift: in std_logic:='0';
data_in: in data2_array(n-1 downto 0);
addr_st: out std_logic;
ram_ad: out std_logic_vector(n-1 downto 0));
END s_term3;

ARCHITECTURE rt1 OF s_term3 IS
SIGNAL addr_st_m:std_logic_vector(n-1 downto 0);
BEGIN
s_term3: FOR i in n-1 downto 0 generate
          uy: p_s1
PORT map(clk,resetn, load, shift, data_in(i), ram_ad(i), addr_st_m(i));
END generate s_term3;
addr_st<=addr_st_m(0) and addr_st_m(1) and addr_st_m(2);
END rt1;