www.pudn.com > equlizer.rar > s_term1.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.equ_pak.all;

ENTITY s_term1 IS
GENERIC(n: positive:=3);
PORT(clk: in std_logic;
resetn: in std_logic:='1';
load:in std_logic:='0';
shift: in std_logic:='0';
data_in: in data1_array(n-1 downto 0);
addr_st: out std_logic;
ram_ad: out std_logic_vector(n-1 downto 0));
END s_term1;

ARCHITECTURE rt1 OF s_term1 IS
SIGNAL addr_st_m:std_logic_vector(n-1 downto 0);
BEGIN
s_term: FOR i in n-1 downto 0 generate
ux: p_s generic map(n=>12)
PORT
map(clk,resetn, load, shift, data_in(i), ram_ad(i), addr_st_m(i));
END generate s_term;
addr_st<=addr_st_m(0) and addr_st_m(1) and addr_st_m(2);
END rt1;