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library ieee; 
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all; 
 
entity mult3 is 
generic(a1:natural; 
        b1:natural; 
        q1:natural); 
 port(clk:in std_logic; 
      resetn:in std_logic; 
      x_in:in std_logic_vector(a1-1 downto 0); 
      y_in:in std_logic_vector(b1-1 downto 0); 
      mult_en:in std_logic; 
      dataout:out std_logic_vector(q1-1 downto 0) 
); 
end mult3; 
 
architecture rtl of mult3 is 
begin 
 process(clk,resetn) 
 variable count:integer range 0 to a1; 
 variable pa:signed((a1+b1) downto 0); 
 variable a_1:std_logic; 
 alias p:signed(b1 downto 0)is 
 pa((a1+b1)downto a1); 
 
begin 
  if resetn='0' then 
    dataout<=(others=>'0');                
  elsif clk'event and clk='1' then              
  if mult_en='1' then 
  p:=(others=>'0'); 
  pa(a1-1 downto 0):=signed(x_in); 
  a_1:='0'; 
  count:=a1; 
 
 elsif count>0 then 
    case std_logic_vector'(pa(0),a_1)is 
    when "01"=> 
    p:=p+signed(y_in); 
    when"10"=> 
    p:=p-signed(y_in); 
    when others=>null; 
  end case; 
    a_1:=pa(0); 
    pa:=shift_right(pa,1); 
    count:=count-1; 
  end if; 
 end if; 
    
 dataout<=std_logic_vector(pa(a1+b1-1 downto 2)); 
  
 end process; 
end architecture rtl;