www.pudn.com > equlizer.rar > filter_con.vhd

 library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
use work.equ_pak.all; 
 
   entity filter_con is 
           port( 
            clk:in std_logic; 
            resetn:in std_logic:='1'; 
            ad_end:in std_logic:='0'; 
            shift_en:out std_logic; 
            load:out std_logic; 
             shift_s12:out std_logic; 
            shift_s3:out std_logic 
          ); 
end filter_con; 
 
  architecture rtl of filter_con is 
    signal shiften_m1,shiften_m2,shiften_m:std_logic; 
         signal load_m:std_logic; 
       signal shiftm1,shiftm2,shiftm3,shiftm4,shiftm5,shiftm6:std_logic; 
       signal shiftm7,shiftm8,shiftm9,shiftm10,shiftm11:std_logic; 
  begin 
    process(clk,resetn) 
      begin 
        if resetn='0' then  
            shift_en<='0'; 
               load<='0'; 
             shift_s12<='0'; 
          load_m<='0'; 
          shiften_m1<='0'; 
          shiften_m2<='0'; 
          shiften_m<='0'; 
elsif clk'event and clk='1' then 
        shiften_m1<=ad_end; 
         shiften_m2<= shiften_m1; 
        shift_en<=shiften_m2 xor shiften_m1; 
     shiften_m<=shiften_m2 xor shiften_m1; 
         load<=shiften_m; 
         load_m<=shiften_m; 
          shift_s12<=load_m; 
   end if; 
end process; 
 
process(clk,resetn) 
  begin 
       if resetn='0' then 
            shift_s3<='0'; 
        shiftm1<='0'; 
        shiftm2<='0'; 
        shiftm3<='0'; 
        shiftm4<='0'; 
shiftm5<='0'; 
 shiftm6<='0'; 
shiftm7<='0'; 
shiftm8<='0'; 
shiftm9<='0'; 
shiftm10<='0'; 
shiftm11<='0'; 
      elsif clk'event and clk='1' then 
              shiftm1<=load_m; 
              shiftm2<=shiftm1; 
   shiftm3<=shiftm2; 
   shiftm4<=shiftm3; 
  shiftm5<=shiftm4; 
  shiftm6<=shiftm5; 
  shiftm7<=shiftm6; 
shiftm8<=shiftm7; 
shiftm9<=shiftm8; 
shiftm10<=shiftm9; 
shiftm11<=shiftm10; 
shift_s3<=shiftm1 or shiftm2 or shiftm3 or shiftm4 or shiftm5 or shiftm6 or shiftm7 or shiftm8 or shiftm9 or shiftm10 or shiftm11; 
     end if; 
  end process; 
   end rtl;