www.pudn.com > equlizer.rar > filter_add.vhd

Library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
use work.equ_pak.all; 
 
entity filter_add is 
           port( 
              clk:in std_logic; 
              resetn:in std_logic:='1';   
              filteradd_en1:in std_logic:='0'; 
              filteradd_en2:in std_logic:='0'; 
              filteradd_en3:in std_logic:='0'; 
       xin1:in std_logic_vector(17 downto 0);--17 
       xin2:in std_logic_vector(17 downto 0); 
xin3:in std_logic_vector(17 downto 0); 
add_out:out std_logic_vector(9 downto 0); 
filterend:out std_logic 
 ); 
   end filter_add; 
 
architecture rtl of filter_add is 
   signal xin1m:std_logic_vector(17 downto 0);--17 
   signal xin2m:std_logic_vector(17 downto 0); 
signal xin3m:std_logic_vector(17 downto 0); 
signal filteradd_en1m,filteradd_en2m,filteradd_en3m:std_logic; 
signal filteradd_en,filteradd_enm1,filteradd_enm2:std_logic; 
begin 
process(clk,resetn,xin1,xin2,xin3) 
   variable m1_result:std_logic_vector(18 downto 0); 
     variable m2_result:std_logic_vector(18 downto 0); 
 begin 
    if resetn='0' then 
       add_out<=(others=>'0'); 
               xin1m<=(others=>'0'); 
               xin2m<=(others=>'0'); 
               xin3m<=(others=>'0'); 
filterend<='0'; 
         elsif clk'event and clk='1' then 
xin1m<=xin1; 
         xin2m<=xin1; 
         xin3m<=xin1; 
                  if filteradd_en='1' then 
                    m1_result:='0'&xin1m+xin2m; 
                     m2_result:='0'&m1_result(18 downto 1)+xin3m; 
                         add_out<=m2_result(18 downto 9); 
                                filterend<='1'; 
                     else 
                             add_out<=(others=>'0'); 
                                 filterend<='0'; 
                       end if; 
                  end if; 
             end process; 
   
       process(clk,resetn) 
        begin 
              if resetn='0' then 
                  filteradd_en<='0'; 
filteradd_en1m<='0'; 
filteradd_en2m<='0'; 
filteradd_en3m<='0'; 
filteradd_enm1<='0'; 
filteradd_enm2<='0'; 
                elsif clk'event and clk='1' then 
                  filteradd_en1m<=filteradd_en1; 
                  filteradd_en2m<=filteradd_en2; 
                  filteradd_en3m<=filteradd_en3; 
filteradd_enm1<=filteradd_en1m and filteradd_en2m and filteradd_en3m; 
 filteradd_enm2<=filteradd_enm1; 
         filteradd_en<=filteradd_enm2 xor filteradd_enm1; 
end if; 
             end process; 
        end rtl;