www.pudn.com > equlizer.rar > filter3_coef.vhd

library ieee; 
USE ieee.std_logic_1164.all; 
USE ieee.std_logic_unsigned.all; 
USE work.equ_pak.all; 
 
ENTITY filter3_coef IS 
GENERIC(n: positive:=3); 
PORT(clk: in std_logic; 
resetn: in std_logic:='1'; 
addr_st: in std_logic:='0'; 
ram_ch:in std_logic:='0'; 
ram_addr:in std_logic_vector(n-1 downto 0):="000"; 
ch_addr: in std_logic_vector(n-1 downto 0):="000"; 
data :in std_logic_vector(15 downto 0):=(others=>'0'); 
ram_out:out std_logic_vector(15 downto 0); 
coefout: out std_logic); 
END filter3_coef; 
 
ARCHITECTURE rt1 OF filter3_coef IS 
SIGNAL q_array:coef_array(2**n-1 downto 0); 
SIGNAL data_m:std_logic_vector(15 downto 0); 
SIGNAL write_s:std_logic; 
SIGNAL ramout_tm:std_logic_vector(15 downto 0); 
SIGNAL ram_ch_add:std_logic; 
SIGNAL ch_addr_m1:std_logic_vector(2 downto 0); 
SIGNAL ch_addr_m2:std_logic_vector(2 downto 0); 
SIGNAL datam:std_logic_vector(15 downto 0); 
SIGNAL ram_addrm:std_logic_vector(2 downto 0); 
SIGNAL ch_addrm:std_logic_vector(2 downto 0); 
SIGNAL addr_stm,ram_chm:std_logic; 
BEGIN 
writ: process(clk,resetn) 
begin 
if resetn='0' then 
for i in 2**n-1 downto 0 loop 
q_array(i)<=(others=>'0'); 
end loop; 
elsif clk'event and clk='1' then 
if write_s='1' then 
case ch_addr_m2 is 
when "000"=>q_array(0)<=data_m; 
when "001"=>q_array(1)<=data_m; 
when "010"=>q_array(2)<=data_m; 
when "011"=>q_array(3)<=data_m; 
when "100"=>q_array(4)<=data_m; 
when "101"=>q_array(5)<=data_m; 
when "110"=>q_array(6)<=data_m; 
when others=>q_array(7)<=data_m; 
end case; 
end if; 
end if; 
end process; 
read1:process(clk,resetn) 
begin 
if resetn='0' then 
ram_out<=(others=>'0'); 
coefout<='0'; 
ram_addrm<="000"; 
elsif clk'event and clk='1' then 
ram_addrm<=ram_addr; 
if addr_stm='1' and ram_chm='0' then 
case ram_addrm is 
when "000"=>ram_out<=q_array(0); 
when "001"=>ram_out<=q_array(1); 
when "010"=>ram_out<=q_array(2); 
when "011"=>ram_out<=q_array(3); 
when "100"=>ram_out<=q_array(4); 
when "101"=>ram_out<=q_array(5); 
when "110"=>ram_out<=q_array(6); 
when others=>ram_out<=q_array(7); 
end case; 
coefout<='1'; 
else 
ram_out<=(others=>'0'); 
coefout<='0'; 
end if; 
end if; 
end process; 
 
read2: process(clk, resetn) 
begin 
if resetn='0' then 
ramout_tm<=(others=>'0'); 
ch_addr_m1<=(others=>'0'); 
ch_addrm<="000"; 
elsif clk'event and clk='1' then 
if ram_chm='1' then 
ch_addrm<=ch_addr; 
case ch_addrm is 
when "000"=>ramout_tm<=q_array(0); 
when "001"=>ramout_tm<=q_array(1); 
when "010"=>ramout_tm<=q_array(2); 
when "011"=>ramout_tm<=q_array(3); 
when "100"=>ramout_tm<=q_array(4); 
when "101"=>ramout_tm<=q_array(5); 
when "110"=>ramout_tm<=q_array(6); 
when others=>ramout_tm<=q_array(7); 
end case; 
ch_addr_m1<=ch_addrm; 
else 
ramout_tm<=(others=>'0'); 
ch_addr_m1<=(others=>'0'); 
end if; 
end if; 
end process; 
 
 
addpro:process(clk,resetn) 
variable m_result:std_logic_vector(16 downto 0); 
begin 
if resetn='0' then 
write_s<='0'; 
data_m<=(others=>'0'); 
ch_addr_m2<=(others=>'0'); 
ram_ch_add<='0'; 
datam<=(others=>'0'); 
elsif clk'event and clk='1' then 
ram_ch_add<=ram_ch; 
ch_addr_m2<=ch_addr_m1; 
datam<=data; 
if ram_ch_add='1' then 
m_result:='0'&ramout_tm+datam; 
data_m<=m_result(16 downto 1); 
write_s<='1'; 
else 
data_m<=(others=>'0'); 
write_s<='0'; 
end if; 
end if; 
end process; 
 
 
 
process(clk,resetn) 
begin 
if resetn='0' then 
addr_stm<='0'; 
ram_chm<='0'; 
elsif clk'event and clk='1' then 
addr_stm<=addr_st; 
ram_chm<=ram_ch; 
end if; 
end process; 
end rt1;