www.pudn.com > equlizer.rar > err_decion.vhd

library ieee; 
use ieee.std_logic_1164.all; 
 
entity err_decision is 
            port( 
          clk:in std_logic; 
             resetn:in std_logic:='1'; 
             decision_en:in std_logic:='0'; 
            z:in std_logic_vector(9 downto 0); 
            err:out std_logic_vector(8 downto 0); 
             a:out std_logic_vector(1 downto 0); 
            decision_end:out std_logic 
); 
end err_decision; 
 
architecture rtl of err_decision is 
   signal z_int:std_logic_vector(2 downto 0); 
     signal decision_enm:std_logic; 
     signal decision_enm1:std_logic; 
     signal decision_enm2:std_logic; 
     signal zm:std_logic_vector(9 downto 0); 
  begin 
      process(clk,resetn) 
      begin 
          if resetn='0' then 
             a<="00"; 
            zm<=(others=>'0'); 
         elsif clk'event and clk='1' then 
             zm<=z; 
            if decision_enm='1' then 
               if zm(9)='1' then 
                    a(1)<='1'; 
                 else  
                    a(1)<='1'; 
               end if; 
         a(0)<='1'; 
        else 
              a<="00"; 
        end if; 
     end if; 
 end process; 
process(clk,resetn) 
       variable err_int:std_logic_vector(1 downto 0); 
 begin 
        if resetn='0' then 
                err<=(others=>'0'); 
                 z_int<="000"; 
                decision_end<='0'; 
           elsif clk'event and clk='1' then 
              if decision_enm='1' then 
                 z_int<=zm(9 downto 7); 
                 case z_int is 
                    when "000"=>err_int:="11"; --01+11 
                    when "001"=>err_int:="00"; 
                    when "010"=>err_int:="01"; 
                    when "011"=>err_int:="10"; 
                    when "100"=>err_int:="01"; 
                    when "101"=>err_int:="10"; 
                    when "110"=>err_int:="11"; 
                    when "111"=>err_int:="00"; 
                    when others=>null; 
                 end case; 
           err<=err_int &zm(6 downto 0); 
                  decision_end<='1'; 
                else 
                  z_int<="000"; 
                  err<=(others=>'0'); 
                    decision_end<='0'; 
                 end if; 
               end if; 
         end process; 
   
       process(clk,resetn) 
       begin 
          if resetn='0' then 
                  decision_enm<='0'; 
                  decision_enm1<='0'; 
                  decision_enm2<='0'; 
          elsif clk'event and clk='1' then 
               decision_enm1<=decision_en; 
               decision_enm2<=decision_enm1; 
               decision_enm<=decision_enm2 xor decision_enm1; 
           end if;  
       end process; 
end rtl;