www.pudn.com > equlizer.rar > equ_pak.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
package equ_pak is
subtype l_byte is std_logic_vector(11 downto 0);
type std_togic_2d is array(natural range<>)of std_logic_vector(2 downto 0);
type coefadd_array is array(natural range<>)of std_logic_vector(17 downto 0);
type coef_array is array(natural range<>)of std_logic_vector(15 downto 0);
type coef_array2 is array(natural range<>)of std_logic_vector(8 downto 0);
type data1_array is array(natural range<>)of std_logic_vector(11 downto 0);
type data2_array is array(natural range<>) of std_logic_vector(1 downto 0);
type y_array is array(natural range 11 downto 0) of std_logic_vector(3 downto 0);
component p_s
generic(n:positive);
port(clk:in std_logic;
resetn:in std_logic:='1';
load_n:in std_logic:='0';
shift_en:in std_logic:='0';
parallel_in:in std_logic_vector(n-1 downto 0);
serial_out:out std_logic;
addr_st:out std_logic);
end component;
component s_term1
generic(n:positive :=3);
port(clk:in std_logic;
resetn:in std_logic:='1';
load:in std_logic:='0';
shift:in std_logic:='0' ;
data_in:in data1_array(n-1 downto 0);
addr_st:out std_logic;
ram_ad:out std_logic_vector(n-1 downto 0));
end component;
component filter_shift
port(clk:in std_logic;
resetn:in std_logic:='1';
xin:in std_logic_vector(11 downto 0);
a:in std_logic_vector(1 downto 0):="00";
s_en:in std_logic:='0' ;
y_ff:out data1_array(2 downto 0);
y_main:out std_logic_vector(11 downto 0);
y_bf : out data2_array(2 downto 0));
end component;
component filter_coef
generic(n:positive :=3);
port(
clk :in std_logic;
resetn:in std_logic :='1';
addr_st:in std_logic:='0' ;
ram_ch:in std_logic:='0' ;
ram_addr:in std_logic_vector(n-1 downto 0):="000";
ch_addr:in std_logic_vector(n-1 downto 0):="000";
data:in std_logic_vector(15 downto 0):=(others=>'0');
ram_out:out std_logic_vector(15 downto 0);
coefout:out std_logic);
end component;
component accumulator
generic(n:positive:=12);
port(
clk:in std_logic;
resetn:in std_logic:='1';
datain:in std_logic_vector(15 downto 0);
f_en : in std_logic:='0';
add_end:out std_logic;
dataout:out std_logic_vector(17 downto 0));
end component;
component filter_add
port(
clk:in std_logic;
resetn:in std_logic:='1' ;
filteradd_en1:in std_logic:='0';
filteradd_en2:in std_logic:='0';
filteradd_en3:in std_logic:='0';
xin1:in std_logic_vector(17 downto 0);--17
xin2:in std_logic_vector(17 downto 0);
xin3:in std_logic_vector(17 downto 0);
add_out:out std_logic_vector(9 downto 0);
filterend:out std_logic);
end component;
component shift_4
port(clk,resetn,d_in:in std_logic;
shift_en:in std_logic;
shift_out0:out std_logic;
shift_out1:out std_logic;
shift_out2:out std_logic;
shift_out3:out std_logic);
end component;
component shift_3
port(clk,resetn,d_in:in std_logic;
shift_en:in std_logic;
shift_out0:out std_logic;
shift_out1:out std_logic;
shift_out2:out std_logic);
end component;
component err_decision
port(
clk:in std_logic;
resetn:in std_logic:='1';
decision_en:in std_logic:='0';
z:in std_logic_vector(9 downto 0);
err:out std_logic_vector(8 downto 0);
a:out std_logic_vector(1 downto 0);
decision_end:out std_logic );
end component;
component adjust1_mult
port(
clk:in std_logic;
resetn:in std_logic:='1';
xin: in data1_array(2 downto 0);
f_zn: in std_logic_vector(8 downto 0);
cmp1_en :in std_logic:='0';
mult_en :in std_logic:='0';
cmp2_en :in std_logic:='0';
addrgene_en:in std_logic:='0';
w_addr:out std_logic_vector(2 downto 0);
data :out std_logic_vector(15 downto 0);
ram_ch:out std_logic);
end component;
component cmplcode
generic(n:positive:=8);
port(a:in std_logic_vector(n-1 downto 0);
b:out std_logic_vector(n-1 downto 0));
end component;
component mult
generic(m:positive:=3;
n:positive:=4);
port(
b_port:in std_logic_vector(m-1 downto 0);
a_port:in std_logic_vector(n-1 downto 0);
product:out std_logic_vector(n+m-1 downto 0));
end component;
component s_term2
generic(n:positive:=12);
port(clk:in std_logic;
resetn:in std_logic:='1';
load_n:in std_logic:='0';
shift_en:in std_logic:='0';
parallel_in:in std_logic_vector(n-1 downto 0);
addr_st:out std_logic;
serial_out:out std_logic);
end component;
component s_term3
generic(n:positive:=3);
port(clk:in std_logic;
resetn:in std_logic:='1';
load:in std_logic:='0';
shift:in std_logic:='0';
data_in:in data2_array(n-1 downto 0);
addr_st:out std_logic;
ram_ad:out std_logic_vector(n-1 downto 0));
end component;
component filter_coef1
port(
clk:in std_logic;
resetn:in std_logic:='1';
addr_st:in std_logic:='0';
ram_ch:in std_logic:='0';
ram_addr:in std_logic:='0';
ch_addr:in std_logic:='0';
data:in std_logic_vector(15 downto 0):=(others=>'0');
ram_out:out std_logic_vector(15 downto 0);
coefout:out std_logic);
end component;
component filter_con
port(
clk:in std_logic;
resetn:in std_logic:='1';
ad_end:in std_logic:='0';
shift_en:out std_logic;
load:out std_logic;
shift_s12:out std_logic;
shift_s3:out std_logic);
end component ;
component adjust2_mult
port(
clk:in std_logic;
resetn:in std_logic:='1';
xin:in std_logic_vector(11 downto 0);
f_zn:in std_logic_vector(8 downto 0);
cmp1_en:in std_logic:='0';
mult_en:in std_logic:='0';
cmp2_en:in std_logic:='0';
addrgene_en:in std_logic:='0';
w_addr:out std_logic;
data:out std_logic_vector(15 downto 0);
ram_ch:out std_logic
);
end component;
component adjust3_mult
port(
clk:in std_logic;
resetn:in std_logic:='0';
xin:in data2_array(2 downto 0);
f_zn:in std_logic_vector(8 downto 0);
cmp1_en:in std_logic:='0';
mult_en:in std_logic:='0';
cmp2_en:in std_logic:='0';
addrgene_en:in std_logic:='0';
w_addr:out std_logic_vector(2 downto 0);
data:out std_logic_vector(8 downto 0);
ram_ch:out std_logic
);
end component;
component filter
port(
clk:in std_logic;
resten:in std_logic:='1';
ad_end:in std_logic:='0';
xin:in std_logic_vector(11 downto 0);
a:in std_logic_vector(1 downto 0);
z:out std_logic_vector(17 downto 0);
x_ff:out data1_array(2 downto 0);
x_main:out std_logic_vector(11 downto 0);
x_bf:out data2_array(2 downto 0);
filterend:out std_logic;
w_addr1:in std_logic_vector(2 downto 0):=(others=>'0');
w_addr2:in std_logic:='0';
w_addr3:in std_logic_vector(2 downto 0):="000";
data1,data2:in std_logic_vector(15 downto 0):=(others=>'0');
data3:in std_logic_vector(8 downto 0):=(others=>'0');
ram_ch1,ram_ch2,ram_ch3:in std_logic:='0'
);
end component;
component adjust
port(
clk:in std_logic;
resten:in std_logic:='1';
ad_end:in std_logic:='0';
xin1:in data1_array(2 downto 0);
xin2:in std_logic_vector(11 downto 0);
xin3:in data2_array(2 downto 0);
f_zn:in std_logic_vector(8 downto 0);
w_addr1:out std_logic_vector(2 downto 0);
w_addr2:out std_logic;
w_addr3:out std_logic_vector(2 downto 0);
data1,data2:out std_logic_vector(15 downto 0);
data3:out std_logic_vector(8 downto 0);
ram_ch1,ram_ch2,ram_ch3:out std_logic
);
end component;
component count
port(
clk:in std_logic;
resten:in std_logic:='1';
shift_end1:in std_logic:='0';
shift_end2:in std_logic:='0';
ram_st:in std_logic:='0';
count_s:out std_logic_vector(3 downto 0)
);
end component;
component count3
port(
clk:in std_logic;
resten:in std_logic:='1';
multend:in std_logic:='0';
address:out std_logic_vector(2 downto 0)
);
end component;
component mult1
port(
clk:in std_logic;
resten:in std_logic:='1';
cmp_xin:in data2_array(2 downto 0);
cmp_f_zn:in std_logic_vector(8 downto 0);
mult_en:in std_logic:='0';
temp1_data:out coef_array2(2 downto 0)
);
end component;
component p_s1
PORT(clk: in std_logic;
resetn: in std_logic:='1';
load_n:in std_logic:='0';
shift_en: in std_logic:='0';
parallel_in : in std_logic_vector(1 downto 0);
serial_out: out std_logic;
addr_st: out std_logic);
END component;
component mult2
generic(a1:natural:=9;
b1:natural:=12;
q1:natural:=16);
port(clk:in std_logic;
resetn:in std_logic:='1';
x_in:in std_logic_vector(a1-1 downto 0);
y_in:in std_logic_vector(b1-1 downto 0);
mult_en:in std_logic;
dataout:out std_logic_vector(q1-1 downto 0)
);
end component;
component mult3
generic(a1:natural:=2;
b1:natural:=9;
q1:natural:=9);
port(clk:in std_logic;
resetn:in std_logic:='1';
x_in:in std_logic_vector(a1-1 downto 0);
y_in:in std_logic_vector(b1-1 downto 0);
mult_en:in std_logic;
dataout:out std_logic_vector(q1-1 downto 0)
);
end component;
component cmplcode2
generic (n:positive:=9);
port (clk:in std_logic;
resetn:in std_logic;
cmpl_en:in std_logic;
xin:in std_logic_vector(n-1 downto 0);
cmp_xin:out std_logic_vector(n-1 downto 0)
);
end component;
component adjust_con
port(
clk:in std_logic;
resetn:in std_logic:='1';
adjust_en:in std_logic:='0';
cmp1_en1:out std_logic;
mult_en1: out std_logic;
cmp2_en1:out std_logic;
addrgene_en1:out std_logic;
cmp1_en2:out std_logic;
mult_en2: out std_logic;
cmp2_en2:out std_logic;
addrgene_en2:out std_logic;
cmp1_en3:out std_logic;
mult_en3: out std_logic;
cmp2_en3:out std_logic;
addrgene_en3:out std_logic
);
end component;
component filter3_coef
generic(n:positive:=3);
port(
clk:in std_logic;
resetn:in std_logic:='1';
addr_st:in std_logic:='0';
ram_ch:in std_logic:='0';
ram_addr:in std_logic_vector(n-1 downto 0):="000";
ch_addr:in std_logic_vector(n-1 downto 0):="000";
data:in std_logic_vector(15 downto 0):=(others=>'0');---15
ram_out:out std_logic_vector(15 downto 0);
coefout:out std_logic
);
end component;
function multp(x:in std_logic_vector;
y:in std_logic_vector)return std_logic_vector;
end equ_pak;
package body equ_pak is
function multp(x:in std_logic_vector;
y:in std_logic_vector)return std_logic_vector is
variable a:std_logic_vector(x'length-1 downto 0);
variable b:std_logic_vector(y'length-1 downto 0);
variable c:std_logic_vector(y'length downto 0);
variable count:integer range 0 to x'length;
variable product:std_logic_vector(x'length+y'length-1 downto 0);
begin
a:=x;
b:=y;
count:=0;
c:=(others=>'0');
while count