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library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
 
entity cmplcode2 is 
    generic (n:positive:=9); 
    port (clk:in std_logic; 
          resetn:in std_logic; 
          cmpl_en:in std_logic; 
          xin:in std_logic_vector(n-1 downto 0); 
          cmp_xin:out std_logic_vector(n-1 downto 0) 
); 
end cmplcode2; 
 
architecture rtl of cmplcode2 is 
     signal cmpl_en_m:std_logic; 
     begin 
       process(clk,resetn) 
          variable xin_tem:std_logic_vector(n-1 downto 0); 
         begin 
        if resetn='0' then 
           cmpl_en_m<='0'; 
        elsif clk'event and clk='1' then 
           cmpl_en_m<=cmpl_en; 
           if cmpl_en_m='1' then 
               xin_tem:=not xin; 
               xin_tem:=xin_tem+1; 
           end if; 
       end if; 
           cmp_xin<=xin_tem; 
end process; 
end rtl;