www.pudn.com > equlizer.rar > adjust.vhd

library ieee; 
use ieee.std_logic_1164.all; 
use work.equ_pak.all; 
 
entity adjust is 
          port( 
             clk:in std_logic; 
             resetn:in std_logic:='1'; 
             adjust_en:in std_logic:='0'; 
             xin1:in data1_array(2 downto 0); 
             xin2:in std_logic_vector(11 downto 0); 
             xin3:in data2_array(2 downto 0); 
             f_zn:in std_logic_vector(8 downto 0); 
            
            w_addr1:out std_logic_vector(2 downto 0); 
            w_addr2:out std_logic; 
            w_addr3:out std_logic_vector(2 downto 0); 
 
            data1,data2:out std_logic_vector(15 downto 0); 
            data3:out std_logic_vector(8 downto 0); 
            ram_ch1,ram_ch2,ram_ch3:out std_logic 
      ); 
  end adjust; 
    
  architecture rtl of adjust is 
     signal cmp1_en1,mult_en1,cmp2_en1,addrgene_en1:std_logic; 
     signal cmp1_en2,mult_en2,cmp2_en2,addrgene_en2:std_logic; 
     signal cmp1_en3,mult_en3,cmp2_en3,addrgene_en3:std_logic; 
begin 
     u0:adjust_con port map(clk,resetn,adjust_en,cmp1_en1,mult_en1,cmp2_en1,addrgene_en1, cmp1_en2,mult_en2,cmp2_en2,addrgene_en2, cmp1_en3,mult_en3,cmp2_en3,addrgene_en3); 
     u1:adjust1_mult port map(clk,resetn,xin1,f_zn,cmp1_en1,mult_en1,cmp2_en1,addrgene_en1,w_addr1,data1,ram_ch1); 
u2:adjust2_mult  port map(clk,resetn, xin2, f_zn,cmp1_en2,mult_en2,cmp2_en2,addrgene_en2,w_addr2,data2,ram_ch2); 
u3:adjust3_mult  port map(clk,resetn, xin3, f_zn,cmp1_en3,mult_en3,cmp2_en3,addrgene_en3,w_addr3,data3,ram_ch3 
); 
end rtl;