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* File: vc5402.h *
* Include file with CPU/Periperal register declarations *
.mmregs ; Include reserved words
;C54x CPU Memory-Mapped Registers
*IMR 0000H Interrupt mask register
*IFR 0001H Interrupt flag register
* 0002H~0005H Reserved
*ST0 0006H Status 0 register
*ST1 0007H Status 1 register
*AL 0008H A accumulator low (A [15:0])
*AH 0009H A accumulator high (A [31:16])
*AG 000AH A accumulator guard (A [39:32])
*BL 000BH B accumulator low (B [15:0])
*BH 000CH B accumulator high (B [31:16])
*BG 000DH B accumulator guard (B [39:32])
*T 000EH Temporary register
*TRN 000FH Transition register
*BK 0019H Circular size register
*BRC 001AH Block repeat counter
*RSA 001BH Block repeat start address
*REA 001CH Block repeat end address
*PMST 001DH PMST register
*XPC 001EH Extended memory map register
* 001FH Reserved
;C54x Peripheral Memory-Mapped Registers
*DRR0 0020H Data receive register 0
*BDRR 0020H Data receive register
*BDDR0 0020H BSP0 data receive register
*DRR 0020H Data receive register
*DXR0 0021H Data transmit register 0
*BDXR 0021H Data transmit register
*BDXR0 0021H Data transmit register
*DXR 0021H Data transmit register
*SPC0 0022H Serial port control register 0
*BSPC 0022H Serial port control register
*SPC 0022H Serial port control register
*BSPCE 0023H BSP control extension register
*BSPCE0 0023H BSP control extension register
*SPCE 0023H BSP control extension register
*TIM 0024H Timer register
*PRD 0025H Period register
*TCR 0026H Timer control register
*PDWSR 0028H Program/data S/W wait-state register
*SWWSR 0028H Program/data S/W wait-state register
*IOWSR 0029H Bank-switching control register
*BSCR 0029H Bank-switching control register
*HPIC 002CH HPI control register
*DRR1 0030H Data receive register 1
*TRCV 0030H Data receive register
*DXR1 0031H Data transmit register 1
*TDXR 0031H Data transmit register
*SPC1 0032H Serial port control register 1
*TSPC 0032H Serial port control register
*TRAD 0035H TDM receive address register
*AXR 0038H ABU transmit address register
*TCSR 0033H TDM channel select register
*TRTA 0034H TDM receive/transmit register
*AXR0 0038H ABU transmit address register
*ARX 0038H ABU transmit address register
*BKX 0039H ABU transmit buffer size register
*BKX0 0039H ABU transmit buffer size register
*ARR 003AH ABU receive address register
*ARR0 003AH ABU receive address register
*BKR 003BH ABU receive buffer size register
*AXR1 003CH ABU transmit address register
*BKX1 003DH ABU transmit buffer size register
*ARR1 003EH ABU receive address register
*BKR1 003FH ABU receive buffer size register
*BDRR1 0040H BSP data receive register
*BDXR1 0041H Data transmit register
*BSPC1 0042H BSP control register
*BSPCE1 0043H BSP control extension register
*CLKMD 0058H Clock modes register
;VC5402 McBSP Memory-Mapped register declarations
DRR20 .set 0020H ;McBSP0 data receive register 2
DRR10 .set 0021H ;McBSP0 data receive register 1
DXR20 .set 0022H ;McBSP0 data transmit register 2
DXR10 .set 0023H ;McBSP0 data transmit register 1
SPSA0 .set 0038H ;McBSP0 serial port sub-bank address register
SPSD0 .set 0039H ;McBSP0 serial port sub-bank data register
DRR21 .set 0040H ;McBSP1 data receive register 2
DRR11 .set 0041H ;McBSP1 data receive register 1
DXR21 .set 0042H ;McBSP1 data transmit register 2
DXR11 .set 0043H ;McBSP1 data transmit register 1
SPSA1 .set 0048H ;McBSP1 serial port sub-bank address register
SPSD1 .set 0049H ;McBSP1 serial port sub-bank data register
;VC5402 McBSP Control Register Sub-Address
SPCR1x .set 0000H ;Serial port control register 1
SPCR2x .set 0001H ;Serial port control register 2
RCR1x .set 0002H ;Receive control register 1
RCR2x .set 0003H ;Receive control register 2
XCR1x .set 0004H ;Transmit control register 1
XCR2x .set 0005H ;Transmit control register 2
SRGR1x .set 0006H ;Sample rate generator register 1
SRGR2x .set 0007H ;Sample rate generator register 2
MCR1x .set 0008H ;Multichannel register 1
MCR2x .set 0009H ;Multichannel register 2
RCERAx .set 000AH ;Receive channel enable register partition A
RCERBx .set 000BH ;Receive channel enable register partition B
XCERAx .set 000CH ;Transmit channel enable register partition A
XCERBx .set 000DH ;Transmit channel enable register partition B
PCRx .set 000EH ;Pin control register
;VC5402 Timer 1 Memory-Mapped register declarations
TIM1 .set 0030H ;Timer1 register
PRD1 .set 0031H ;Timer1 period register
TCR1 .set 0032H ;Timer1 control register
;VC5402 General Purpose I/O Control register declarations
GPIOCR .set 003CH ;General purpose I/O pins control register
GPIOSR .set 003DH ;General purpose I/O pins status register
;VC5402 DMA Memory-Mapped register declarations
DMPREC .set 0054H ;DMA channel priority and enable control register
DMSA .set 0055H ;DMA sub-bank address register
DMSDI .set 0056H ;DMA sub-bank data register with sub-bank address auto-increment
DMSDN .set 0057H ;DMA sub-bank data register
;VC5402 DMA Control Register Sub-Address
DMSRC0 .set 0000H ;DMA channel 0 source address register
DMDST0 .set 0001H ;DMA channel 0 destination address register
DMCTR0 .set 0002H ;DMA channel 0 element count register
DMSFC0 .set 0003H ;DMA channel 0 sync select and frame count register
DMMCR0 .set 0004H ;DMA channel 0 transfer mode control register
DMSRC1 .set 0005H ;DMA channel 1 source address register
DMDST1 .set 0006H ;DMA channel 1 destination address register
DMCTR1 .set 0007H ;DMA channel 1 element count register
DMSFC1 .set 0008H ;DMA channel 1 sync select and frame count register
DMMCR1 .set 0009H ;DMA channel 1 transfer mode control register
DMSRC2 .set 000AH ;DMA channel 2 source address register
DMDST2 .set 000BH ;DMA channel 2 destination address register
DMCTR2 .set 000CH ;DMA channel 2 element count register
DMSFC2 .set 000DH ;DMA channel 2 sync select and frame count register
DMMCR2 .set 000EH ;DMA channel 2 transfer mode control register
DMSRC3 .set 000FH ;DMA channel 3 source address register
DMDST3 .set 0010H ;DMA channel 3 destination address register
DMCTR3 .set 0011H ;DMA channel 3 element count register
DMSFC3 .set 0012H ;DMA channel 3 sync select and frame count register
DMMCR3 .set 0013H ;DMA channel 3 transfer mode control register
DMSRC4 .set 0014H ;DMA channel 4 source address register
DMDST4 .set 0015H ;DMA channel 4 destination address register
DMCTR4 .set 0016H ;DMA channel 4 element count register
DMSFC4 .set 0017H ;DMA channel 4 sync select and frame count register
DMMCR4 .set 0018H ;DMA channel 4 transfer mode control register
DMSRC5 .set 0019H ;DMA channel 5 source address register
DMDST5 .set 001AH ;DMA channel 5 destination address register
DMCTR5 .set 001BH ;DMA channel 5 element count register
DMSFC5 .set 001CH ;DMA channel 5 sync select and frame count register
DMMCR5 .set 001DH ;DMA channel 5 transfer mode control register
DMSRCP .set 001EH ;DMA source program page address (common channel)
DMDSTP .set 001FH ;DMA destination program page address (common channel)
DMIDX0 .set 0020H ;DMA element index address register 0
DMIDX1 .set 0021H ;DMA element index address register 1
DMFRI0 .set 0022H ;DMA frame index register 0
DMFRI1 .set 0023H ;DMA frame index register 1
DMGSA .set 0024H ;DMA global source address reload register
DMGDA .set 0025H ;DMA global destination address reload register
DMGCR .set 0026H ;DMA global count reload register
DMGFR .set 0027H ;DMA global frame count reload register
;VC5402 Software Wait-State Control Register
SWCR .set 002BH ;Software Wait-State Control Register