www.pudn.com > jaguar2s.zip > Ram2rw256xM.vhd

--************************************************************ 
--************************************************************ 
--*----------------------------------------------------------* 
--*|Version                          :1.0                    | 
--*|Date of Last Revision            :12/23/1998             | 
--*----------------------------------------------------------* 
--************************************************************ 
-- Copyright (C) 1999 Drey Enterprises.   All Rights Reserved. 
--************************************************************ 
-- Warning: This file is protected by Federal Copyright Law, 
-- with all rights reserved. It is unlawful to reproduce 
-- any parts of this file, in any form, without expressed 
-- written permission from Drey Enterprises. This Copyright 
-- is actively enforced. 
--************************************************************ 
--************************************************************ 
 
library IEEE; 
use IEEE.std_logic_1164.all; 
use IEEE.std_logic_unsigned.all; 
 
entity RAM2RW256xM is 
    generic( 
        WORD_WIDTH     :integer := 32 -- unused for xilinx 
    ); 
    port( 
        clk            :in std_logic; 
        pass           :in std_logic_vector(3 downto 0); -- unused except in altera 
        wea            :in std_logic; 
        web            :in std_logic; 
        addra          :in std_logic_vector(7 downto 0); 
        addrb          :in std_logic_vector(7 downto 0); 
        dataina        :in std_logic_vector(31 downto 0); 
        datainb        :in std_logic_vector(31 downto 0); 
        dataouta       :out std_logic_vector(31 downto 0); 
        dataoutb       :out std_logic_vector(31 downto 0) 
     ); 
end RAM2RW256xM; 
 
architecture behavior of RAM2RW256xM is 
 
    component RAMB4_S16_S16 
    port( 
        CLKA           :in std_logic; 
        CLKB           :in std_logic; 
        WEA            :in std_logic; 
        WEB            :in std_logic; 
        ENA            :in std_logic; 
        ENB            :in std_logic; 
        RSTA           :in std_logic; 
        RSTB           :in std_logic; 
        ADDRA          :in std_logic_vector(7 downto 0); 
        ADDRB          :in std_logic_vector(7 downto 0); 
        DIA            :in std_logic_vector(15 downto 0); 
        DIB            :in std_logic_vector(15 downto 0); 
        DOA            :out std_logic_vector(15 downto 0); 
        DOB            :out std_logic_vector(15 downto 0) 
     ); 
     end component; 
 
     signal one,gnd         :std_logic; 
 
begin 
     
    gnd <= '0'; 
    one <= '1'; 
 
    u1:RAMB4_S16_S16 
    port map( 
        CLKA => clk, 
        CLKB => clk, 
        WEA => wea, 
        WEB => web, 
        ENA => one, 
        ENB => one, 
        RSTA => gnd, 
        RSTB => gnd, 
        ADDRA => addra, 
        ADDRB => addrb, 
        DIA => dataina(31 downto 16), 
        DIB => datainb(31 downto 16), 
        DOA => dataouta(31 downto 16), 
        DOB => dataoutb(31 downto 16) 
     ); 
 
    u2:RAMB4_S16_S16 
    port map( 
        CLKA => clk, 
        CLKB => clk, 
        WEA => wea, 
        WEB => web, 
        ENA => one, 
        ENB => one, 
        RSTA => gnd, 
        RSTB => gnd, 
        ADDRA => addra, 
        ADDRB => addrb, 
        DIA => dataina(15 downto 0), 
        DIB => datainb(15 downto 0), 
        DOA => dataouta(15 downto 0), 
        DOB => dataoutb(15 downto 0) 
     ); 
 
end behavior;