www.pudn.com > jaguar2s.zip > radix2_4.vhd
--************************************************************
--************************************************************
--*----------------------------------------------------------*
--*|Version :1.0 |
--*|Date of Last Revision :12/23/1998 |
--*----------------------------------------------------------*
--************************************************************
-- Copyright (C) 1999 Drey Enterprises Inc. All Rights Reserved.
--************************************************************
-- Warning: This file is protected by Federal Copyright Law,
-- with all rights reserved. It is unlawful to reproduce
-- any parts of this file, in any form, without expressed
-- written permission from Drey Enterprises Inc. This Copyright
-- is actively enforced.
--************************************************************
--************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
-- NOTE: ROMS are fixed at 32bits wide. This reflects the
-- maximum possible value for WORD_WIDTH. Smaller values
-- for WORD_WIDTH will dissolve that portion of the ROM
-- ie. The ROM doesn't stay that big after synthesis.
-- On each clock cycle, read four values from porta(0..3), and write
-- four values to portb(0..3)
entity radix2_4 is
generic(
WORD_WIDTH :integer := 32
);
port(
clk :in std_logic;
fwd :in std_logic;
null_pass :in std_logic;
rad4 :in std_logic;
W1_sin_data :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
W1_cos_data :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
W2_sin_data :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
W2_cos_data :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
W3_sin_data :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
W3_cos_data :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
datafra0 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datafra1 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datafra2 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datafra3 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datafrb0 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datafrb1 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datatra0 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datatra1 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datatra2 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datatra3 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datatrb0 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datatrb1 :out std_logic_vector(WORD_WIDTH-1 downto 0)
);
end radix2_4;
architecture structure of radix2_4 is
component rad2_4_eval
generic(
WORD_WIDTH :integer
);
port(
clk :in std_logic;
fwd :in std_logic;
rad4 :in std_logic;
W1_sin_data :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
W1_cos_data :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
W2_sin_data :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
W2_cos_data :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
W3_sin_data :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
W3_cos_data :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
A :in std_logic_vector(WORD_WIDTH-1 downto 0);
B :in std_logic_vector(WORD_WIDTH-1 downto 0);
C :in std_logic_vector(WORD_WIDTH-1 downto 0);
D :in std_logic_vector(WORD_WIDTH-1 downto 0);
G0 :out std_logic_vector(WORD_WIDTH-1 downto 0);
G1 :out std_logic_vector(WORD_WIDTH-1 downto 0);
G2 :out std_logic_vector(WORD_WIDTH-1 downto 0);
G3 :out std_logic_vector(WORD_WIDTH-1 downto 0)
);
end component;
signal datatr0 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datatr1 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datatra1_mux :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datatr2 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datatr3 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datafr2 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datafr3 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datafrb0_reg :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datafrb1_reg :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datafrb0_dlyd :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datafrb1_dlyd :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datafra0_reg :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datafra1_reg :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datafra0_dlyd :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datafra1_dlyd :std_logic_vector(WORD_WIDTH-1 downto 0);
begin
process(rad4,datafra2,datafra3,
datafrb0,datafrb1)
begin
if (rad4 = '1') then
datafr2 <= datafra2;
datafr3 <= datafra3;
else -- radix 2
datafr2 <= datafrb0;
datafr3 <= datafrb1;
end if;
end process;
process(null_pass,datatr0,datatra1_mux,datatr1,datatr3,
datafra0_dlyd,datafra1_dlyd,
datafrb0_dlyd,datafrb1_dlyd)
begin
if (null_pass = '1') then
datatra0 <= datafra0_dlyd;
datatra1 <= datafra1_dlyd;
datatrb0 <= datafrb0_dlyd;
datatrb1 <= datafrb1_dlyd;
else
datatra0 <= datatr0;
datatra1 <= datatra1_mux;
datatrb0 <= datatr1;
datatrb1 <= datatr3;
end if;
end process;
process
begin
wait until clk'event and clk = '1';
datafra0_dlyd <= datafra0_reg;
datafra1_dlyd <= datafra1_reg;
datafra0_reg <= datafra0;
datafra1_reg <= datafra1;
datafrb0_dlyd <= datafrb0_reg;
datafrb1_dlyd <= datafrb1_reg;
datafrb0_reg <= datafrb0;
datafrb1_reg <= datafrb1;
end process;
datatra2 <= datatr2;
datatra3 <= datatr3;
process(rad4,datatr1,datatr2)
begin
if (rad4 = '1') then
datatra1_mux <= datatr1;
else -- radix 2
datatra1_mux <= datatr2;
end if;
end process;
rad2_4:rad2_4_eval
generic map(WORD_WIDTH => WORD_WIDTH)
port map(
clk => clk,
fwd => fwd,
rad4 => rad4,
W1_sin_data => W1_sin_data,
W1_cos_data => W1_cos_data,
W2_sin_data => W2_sin_data,
W2_cos_data => W2_cos_data,
W3_sin_data => W3_sin_data,
W3_cos_data => W3_cos_data,
A => datafra0,
B => datafra1,
C => datafr2,
D => datafr3,
G0 => datatr0,
G1 => datatr1,
G2 => datatr2,
G3 => datatr3
);
end structure;