www.pudn.com > jaguar2s.zip > radix2.vhd

--************************************************************ 
--************************************************************ 
--*----------------------------------------------------------* 
--*|Version                           :1.0                   | 
--*|Date of Last Revision             :12/23/1998            | 
--*----------------------------------------------------------* 
--************************************************************ 
-- Copyright (C) 1999 Drey Enterprises Inc.   All Rights Reserved. 
--************************************************************ 
-- Warning: This file is protected by Federal Copyright Law, 
-- with all rights reserved. It is unlawful to reproduce 
-- any parts of this file, in any form, without expressed 
-- written permission from Drey Enterprises Inc. This Copyright 
-- is actively enforced. 
--************************************************************ 
--************************************************************ 
 
library IEEE; 
use IEEE.std_logic_1164.all; 
 
-- two cycles of latency 
-- two bits of attenuation 
 
entity radix2 is 
    generic( 
        WORD_WIDTH        :integer := 32 
    ); 
    port( 
        clk               :in std_logic; 
        fwd               :in std_logic; 
        null_pass         :in std_logic; 
        sin_w             :in std_logic_vector(WORD_WIDTH/2-1 downto 0); 
        cos_w             :in std_logic_vector(WORD_WIDTH/2-1 downto 0); 
        X0                :in std_logic_vector(WORD_WIDTH-1 downto 0); 
        X1                :in std_logic_vector(WORD_WIDTH-1 downto 0); 
        G0                :out std_logic_vector(WORD_WIDTH-1 downto 0); 
        G1                :out std_logic_vector(WORD_WIDTH-1 downto 0) 
    ); 
end radix2; 
 
architecture structure of radix2 is 
 
    component fft_mult 
    generic( 
        WORD_WIDTH        :integer 
    ); 
    port( 
        clk              :in std_logic; 
        fwd              :in std_logic; 
        sin_w            :in std_logic_vector(WORD_WIDTH/2-1 downto 0); 
        cos_w            :in std_logic_vector(WORD_WIDTH/2-1 downto 0); 
        X                :in std_logic_vector(WORD_WIDTH-1 downto 0); 
        Y                :out std_logic_vector(WORD_WIDTH-1 downto 0) 
    ); 
    end component; 
 
    component signed_add 
    generic( 
        WIDTH            :integer 
    ); 
    port( 
        a                :in std_logic_vector(WIDTH-1 downto 0); 
        b                :in std_logic_vector(WIDTH-1 downto 0); 
        c                :out std_logic_vector(WIDTH-1 downto 0) 
    ); 
    end component;   
 
    component signed_sub 
    generic( 
        WIDTH            :integer 
    ); 
    port( 
        a                :in std_logic_vector(WIDTH-1 downto 0); 
        b                :in std_logic_vector(WIDTH-1 downto 0); 
        c                :out std_logic_vector(WIDTH-1 downto 0) 
    ); 
    end component;   
 
    signal G0_sig        :std_logic_vector(WORD_WIDTH-1 downto 0); 
    signal G1_sig        :std_logic_vector(WORD_WIDTH-1 downto 0); 
    signal G0_reg        :std_logic_vector(WORD_WIDTH-1 downto 0); 
    signal G1_reg        :std_logic_vector(WORD_WIDTH-1 downto 0); 
    signal G0_bypass     :std_logic_vector(WORD_WIDTH-1 downto 0); 
    signal G1_bypass     :std_logic_vector(WORD_WIDTH-1 downto 0); 
    signal G0_bypass_reg :std_logic_vector(WORD_WIDTH-1 downto 0); 
    signal G1_bypass_reg :std_logic_vector(WORD_WIDTH-1 downto 0); 
    signal G0_tmp        :std_logic_vector(WORD_WIDTH-1 downto 0); 
    signal G1_tmp        :std_logic_vector(WORD_WIDTH-1 downto 0); 
 
begin  
         
    real_g0:signed_add 
    generic map(WIDTH => WORD_WIDTH/2) 
    port map( 
        a => X0(WORD_WIDTH-1 downto WORD_WIDTH/2), 
        b => X1(WORD_WIDTH-1 downto WORD_WIDTH/2), 
        c => G0_tmp(WORD_WIDTH-1 downto WORD_WIDTH/2) 
    ); 
 
    imag_g0:signed_add 
    generic map(WIDTH => WORD_WIDTH/2) 
    port map( 
        a => X0(WORD_WIDTH/2-1 downto 0), 
        b => X1(WORD_WIDTH/2-1 downto 0), 
        c => G0_tmp(WORD_WIDTH/2-1 downto 0) 
    ); 
 
    real_g1:signed_sub 
    generic map(WIDTH => WORD_WIDTH/2) 
    port map( 
        a => X0(WORD_WIDTH-1 downto WORD_WIDTH/2), 
        b => X1(WORD_WIDTH-1 downto WORD_WIDTH/2), 
        c => G1_tmp(WORD_WIDTH-1 downto WORD_WIDTH/2) 
    ); 
 
    imag_g1:signed_sub 
    generic map(WIDTH => WORD_WIDTH/2) 
    port map( 
        a => X0(WORD_WIDTH/2-1 downto 0), 
        b => X1(WORD_WIDTH/2-1 downto 0), 
        c => G1_tmp(WORD_WIDTH/2-1 downto 0) 
    ); 
 
    g1_mult:fft_mult 
    generic map(WORD_WIDTH => WORD_WIDTH) 
    port map( 
        clk => clk, 
        fwd => fwd, 
        sin_w => sin_w, 
        cos_w => cos_w, 
        X => G1_tmp, 
        Y => G1_sig 
    ); 
 
    --insert some delay on G0 to re-align 
    -- and atten by one bits for conformity 
    process 
    begin 
        wait until clk'event and clk= '1'; 
        G0_reg(WORD_WIDTH-1 downto WORD_WIDTH/2) <=  
                 G0_tmp(WORD_WIDTH-1) &  
                 G0_tmp(WORD_WIDTH-1 downto WORD_WIDTH/2 + 1); 
        G0_reg(WORD_WIDTH/2-1 downto 0) <=  
                 G0_tmp(WORD_WIDTH/2-1) & 
                 G0_tmp(WORD_WIDTH/2-1 downto 1); 
        G0_sig <= G0_reg; 
    end process; 
 
    process(null_pass,X0,X1,G0_sig,G1_sig) 
    begin 
        if (null_pass = '1') then 
            G0 <= G0_bypass; 
            G1 <= G1_bypass; 
        else 
            G0 <= G0_sig; 
            G1 <= G1_sig; 
        end if; 
    end process; 
 
    process 
    begin 
        wait until clk'event and clk= '1'; 
        G0_bypass_reg <= X0; 
        G0_bypass <= G0_bypass_reg; 
        G1_bypass_reg <= X1; 
        G1_bypass <= G1_bypass_reg; 
    end process; 
 
end structure;