www.pudn.com > jaguar2s.zip > rad4_sqncr.vhd

--************************************************************ 
--************************************************************ 
--*----------------------------------------------------------* 
--*|Version                           :1.0                   | 
--*|Date of Last Revision             :12/23/1998            | 
--*----------------------------------------------------------* 
--************************************************************ 
-- Copyright (C) 1999 Drey Enterprises Inc.   All Rights Reserved. 
--************************************************************ 
-- Warning: This file is protected by Federal Copyright Law, 
-- with all rights reserved. It is unlawful to reproduce 
-- any parts of this file, in any form, without expressed 
-- written permission from Drey Enterprises Inc. This Copyright 
-- is actively enforced. 
--************************************************************ 
--************************************************************ 
 
library IEEE; 
use IEEE.std_logic_1164.all; 
use IEEE.std_logic_unsigned.all; 
 
entity rad4_sqncr is 
    port( 
        reset              :in std_logic; 
        core_clk           :in std_logic; 
        N_select           :in std_logic_vector(2 downto 0); 
        startpc            :in std_logic; 
        rad4done           :out std_logic; 
        addr_in            :out std_logic_vector(7 downto 0); 
        addr_out           :out std_logic_vector(7 downto 0); 
        we                 :out std_logic; 
        rom_addr           :out std_logic_vector(7 downto 0) 
    ); 
end rad4_sqncr; 
 
architecture structure of rad4_sqncr is 
 
    component rad4_romaddr_cmpt 
    port( 
        N_select           :in std_logic_vector(2 downto 0); 
        rom_cntr           :in std_logic_vector(7 downto 0); 
        rom_addr           :out std_logic_vector(7 downto 0) 
    ); 
    end component; 
 
    signal TERMCNT         :std_logic_vector(8 downto 0); 
    signal clk_cnt         :std_logic_vector(8 downto 0); 
    signal addr_out_reg    :std_logic_vector(8 downto 0); 
    signal rad4done_reg    :std_logic; 
 
begin  
 
    addr_in <= clk_cnt(7 downto 0); 
 
    adj_rom_addr:rad4_romaddr_cmpt 
    port map( 
        N_select => N_select, 
        rom_cntr => clk_cnt(7 downto 0), 
        rom_addr => rom_addr 
    ); 
 
    process(reset,core_clk) 
    begin 
        if (reset = '0') then 
            clk_cnt <= "000000000"; 
        elsif core_clk'event and core_clk = '1' then 
            if (startpc = '1') then 
                clk_cnt <= "000000000"; 
            elsif (clk_cnt /= "100000011") then 
                clk_cnt <= clk_cnt + "000000001"; 
           end if; 
        end if; 
    end process; 
 
    process(N_select) 
    begin 
        case N_select is  
           when "000" =>  -- 8 point 
               TERMCNT <= "000000100"; 
           when "001" =>  -- 16 point 
               TERMCNT <= "000000110"; 
           when "010" =>  -- 32 point 
               TERMCNT <= "000001010"; 
           when "011" =>  -- 64 point 
               TERMCNT <= "000010010"; 
           when "100" =>  -- 128 point 
               TERMCNT <= "000100010"; 
           when "101" =>  -- 256 point 
               TERMCNT <= "001000010"; 
           when "110" =>  -- 512 point 
               TERMCNT <= "010000010"; 
           when others => -- 1024 point 
               TERMCNT <= "100000010"; 
        end case; 
    end process;     
 
    rad4done <= rad4done_reg; 
    process(reset,core_clk) 
    begin 
        if (reset = '0') then 
            rad4done_reg <= '0'; 
        elsif core_clk'event and core_clk = '1' then 
            if (clk_cnt = TERMCNT) then 
                rad4done_reg <= '1'; 
            else 
                rad4done_reg <= '0'; 
            end if; 
        end if; 
    end process; 
 
    process(reset,core_clk) 
    begin 
        if (reset = '0') then 
            we <= '0'; 
        elsif core_clk'event and core_clk = '1' then 
            if (clk_cnt = "000000010") then 
                we <= '1'; 
            elsif (clk_cnt = TERMCNT) then 
                we <= '0'; 
            end if; 
        end if; 
    end process; 
 
    addr_out <= addr_out_reg(7 downto 0); 
    process(reset,core_clk) 
    begin 
        if (reset = '0') then 
            addr_out_reg <= "000000000"; 
        elsif core_clk'event and core_clk = '1' then 
            if (startpc = '1') then 
                addr_out_reg <= "011111101"; 
            elsif (clk_cnt /= "100000011") then 
                addr_out_reg <= addr_out_reg + "000000001"; 
            end if; 
        end if; 
    end process; 
 
end structure;