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--************************************************************ 
--************************************************************ 
--*----------------------------------------------------------* 
--*|Version                           :1.0                   | 
--*|Date of Last Revision             :12/23/1998            | 
--*----------------------------------------------------------* 
--************************************************************ 
-- Copyright (C) 1999 Drey Enterprises Inc.   All Rights Reserved. 
--************************************************************ 
-- Warning: This file is protected by Federal Copyright Law, 
-- with all rights reserved. It is unlawful to reproduce 
-- any parts of this file, in any form, without expressed 
-- written permission from Drey Enterprises Inc. This Copyright 
-- is actively enforced. 
--************************************************************ 
--************************************************************ 
 
library IEEE; 
use IEEE.std_logic_1164.all; 
use IEEE.std_logic_unsigned.all; 
 
entity rad4_romaddr_cmpt is 
    port( 
        N_select           :in std_logic_vector(2 downto 0); 
        rom_cntr           :in std_logic_vector(7 downto 0); 
        rom_addr           :out std_logic_vector(7 downto 0) 
    ); 
end rad4_romaddr_cmpt; 
 
architecture structure of rad4_romaddr_cmpt is 
 
begin 
    
    process(N_select,rom_cntr) 
    begin 
        case N_select is  
            when "000" => rom_addr <= rom_cntr(0) & "0000000"; 
            when "001" => rom_addr <= rom_cntr(1 downto 0) & "000000"; 
            when "010" => rom_addr <= rom_cntr(2 downto 0) & "00000"; 
            when "011" => rom_addr <= rom_cntr(3 downto 0) & "0000"; 
            when "100" => rom_addr <= rom_cntr(4 downto 0) & "000"; 
            when "101" => rom_addr <= rom_cntr(5 downto 0) & "00"; 
            when "110" => rom_addr <= rom_cntr(6 downto 0) & '0'; 
            when others => rom_addr <= rom_cntr; 
        end case; 
    end process; 
         
end structure;